公开(公告)号：US11579925B2

公开(公告)日：2023-02-14

申请号：US16562364

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Gregory Scott Palmer ,  Jonathon Stuart Ramsey Evans ,  Shailendra Singh ,  Samuel H. Duncan ,  Wishwesh Anil Gandhi ,  Lacky V. Shah ,  Eric Rock ,  Feiqi Su ,  James Leroy Deming ,  Alan Menezes ,  Pranav Vaidya ,  Praveen Joginipally ,  Timothy John Purcell ,  Manas Mandal

IPC: G06F9/46 ,  G06F9/50

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US11249905B2

公开(公告)日：2022-02-15

申请号：US16562361

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Gregory Scott Palmer ,  Jonathon Stuart Ramsey Evans ,  Shailendra Singh ,  Samuel H. Duncan ,  Wishwesh Anil Gandhi ,  Lacky V. Shah ,  Eric Rock ,  Feiqi Su ,  James Leroy Deming ,  Alan Menezes ,  Pranav Vaidya ,  Praveen Joginipally ,  Timothy John Purcell ,  Manas Mandal

IPC: G06F12/06 ,  G06F9/50

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US11893423B2

公开(公告)日：2024-02-06

申请号：US16562367

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Gregory Scott Palmer ,  Jonathon Stuart Ramsey Evans ,  Shailendra Singh ,  Samuel H. Duncan ,  Wishwesh Anil Gandhi ,  Lacky V. Shah ,  Sonata Gale Wen ,  Feiqi Su ,  James Leroy Deming ,  Alan Menezes ,  Pranav Vaidya ,  Praveen Joginipally ,  Timothy John Purcell ,  Manas Mandal

IPC: G06F9/50 ,  G06F9/38 ,  G06F1/3296 ,  G06F1/04

CPC classification number: G06F9/5061 ,  G06F1/04 ,  G06F1/3296 ,  G06F9/3877 ,  G06F9/5027

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US11663036B2

公开(公告)日：2023-05-30

申请号：US16562359

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Gregory Scott Palmer ,  Jonathon Stuart Ramsey Evans ,  Shailendra Singh ,  Samuel H. Duncan ,  Wishwesh Anil Gandhi ,  Lacky V. Shah ,  Eric Rock ,  Feiqi Su ,  James Leroy Deming ,  Alan Menezes ,  Pranav Vaidya ,  Praveen Joginipally ,  Timothy John Purcell ,  Manas Mandal

IPC: G06F9/48 ,  G06F9/46 ,  G06T1/20

CPC classification number: G06F9/485 ,  G06F9/461 ,  G06T1/20

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US10037228B2

公开(公告)日：2018-07-31

申请号：US13660763

申请日：2012-10-25

Applicant: NVIDIA Corporation

Inventor： Nick Barrow-Williams ,  Brian Fahs ,  Jerome F. Duluk, Jr. ,  James Leroy Deming ,  Timothy John Purcell ,  Lucien Dunning ,  Mark Hairgrove

IPC: G06F12/00 ,  G06F9/50 ,  G06F12/1045 ,  G06F12/109

CPC classification number: G06F9/5027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

公开(公告)号：US11635986B2

公开(公告)日：2023-04-25

申请号：US16562359

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Gregory Scott Palmer ,  Jonathon Stuart Ramsey Evans ,  Shailendra Singh ,  Samuel H. Duncan ,  Wishwesh Anil Gandhi ,  Lacky V. Shah ,  Eric Rock ,  Feiqi Su ,  James Leroy Deming ,  Alan Menezes ,  Pranav Vaidya ,  Praveen Joginipally ,  Timothy John Purcell ,  Manas Mandal

IPC: G06F9/48 ,  G06F9/46 ,  G06T1/20

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US10310973B2

公开(公告)日：2019-06-04

申请号：US13660815

申请日：2012-10-25

Applicant: NVIDIA Corporation

Inventor： Nick Barrow-Williams ,  Brian Fahs ,  Jerome F. Duluk, Jr. ,  James Leroy Deming ,  Timothy John Purcell ,  Lucien Dunning ,  Mark Hairgrove

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/1009

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

公开(公告)号：US10169091B2

公开(公告)日：2019-01-01

申请号：US13660799

申请日：2012-10-25

Applicant: NVIDIA Corporation

Inventor： Nick Barrow-Williams ,  Brian Fahs ,  Jerome F. Duluk, Jr. ,  James Leroy Deming ,  Timothy John Purcell ,  Lucien Dunning ,  Mark Hairgrove

IPC: G06F9/46 ,  G06F15/173 ,  G06F9/50 ,  G06F12/1045 ,  G06F9/48 ,  G06F9/455 ,  G06F12/109 ,  G06F12/1036

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

公开(公告)号：US09639466B2

公开(公告)日：2017-05-02

申请号：US13664387

申请日：2012-10-30

Applicant: NVIDIA Corporation

Inventor： James Patrick Robertson ,  Gregory Alan Muthler ,  Hemayet Hossain ,  Timothy John Purcell ,  Karan Mehra ,  Peter B. Holmqvist ,  George R. Lynch

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/0868 ,  G06F12/0866

CPC classification number: G06F12/0804 ,  G06F12/084 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0895

Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty. The technique further involves determining whether a total number of cache lines marked as dirty in the set of cache lines is less than, equal to, or greater than a first threshold value, and: not transmitting a dirty data notification to the frame buffer logic when the total number is less than the threshold value, or transmitting a dirty data notification to the frame buffer logic when the total number is equal to or greater than the first threshold value.

公开(公告)号：US08941653B2

公开(公告)日：2015-01-27

申请号：US14082669

申请日：2013-11-18

Applicant: NVIDIA Corporation

Inventor： Steven E. Molnar ,  Emmett M. Kilgariff ,  John S. Rhoades ,  Timothy John Purcell ,  Sean J. Treichler ,  Ziyad S. Hakura ,  Franklin C. Crow ,  James C. Bowman

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T2210/52

Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

Abstract translation: 本发明的一个实施例提出了一种用于在保持API原语排序的同时并行渲染图形基元的技术。 多个独立的几何单元在不同的图形基元上同时执行几何处理。 原始分配方案以每个时钟的多个基元的速率同时向多个光栅化器提供原语，同时保持每个像素的原始排序。 多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。