公开(公告)号：US20140292287A1

公开(公告)日：2014-10-02

申请号：US14208180

申请日：2014-03-13

Applicant: NXP B.V.

Inventor： Philip RUTTER ,  Maarten SWANENBERG

IPC: G05F1/70

CPC classification number: G05F1/70 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/0883 ,  H03K17/08148 ,  H03K17/567 ,  H03K2017/6875

Abstract: A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.

Abstract translation: 一种半导体器件，包括以共源共栅配置布置的第一和第二场效应晶体管：其中所述第一场效应晶体管是耗尽型晶体管; 并且其中所述第二场效应晶体管包括第一源至栅极电容和第二附加源至栅极电容并联连接到所述第一源至栅极电容。 包括半导体器件的功率因数校正（PFC）电路。 包括PFC电路的电源。

公开(公告)号：US20140145208A1

公开(公告)日：2014-05-29

申请号：US14056648

申请日：2013-10-17

Applicant: NXP B.V.

Inventor： Matthias ROSE ,  Jan SONSKY ,  Philip RUTTER

IPC: H01L27/088 ,  H01L27/08

CPC classification number: H01L27/088 ,  H01L27/0814 ,  H03K17/567 ,  H03K17/6871 ,  H03K17/6874 ,  H03K17/74 ,  H03K2017/6875

Abstract: A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.

Abstract translation: 级联功率半导体电路在氮化镓或碳化硅FET的源极和栅极之间具有钳位电路，以提供共源共栅MOSFET晶体管的雪崩保护。

公开(公告)号：US20140220749A1

公开(公告)日：2014-08-07

申请号：US14249204

申请日：2014-04-09

Applicant: NXP B.V.

Inventor： Philip RUTTER

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L25/072 ,  H01L27/0733 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, a method of may be provided to manufacture a vertical capacitor region that comprises a plurality of said trenches, wherein the portions of the semiconductor region in between said trenches comprise an impurity. This allows for the trenches to be placed in closer vicinity to each other, thus improving the capacitance per unit area ratio. The total capacitance of the device is defined by two series components, that is, the capacitance across the dielectric liner, and the depletion capacitance of the silicon next to the trench. An increase of the voltage on the capacitor increases the depletion in the silicon and the depletion capacitance as a result, such that the overall capacitance is reduced. This effect may be countered by minimizing the depletion region which may be achieved by ensuring that the silicon adjacent to the capacitor is as highly doped as possible.

Abstract translation: 与示例性实施例一致，可以提供一种制造包括多个所述沟槽的垂直电容器区域的方法，其中所述沟槽之间的半导体区域中的部分包括杂质。 这允许将沟槽放置得更靠近彼此，从而改善每单位面积比的电容。 器件的总电容由两个串联组件（即电介质衬垫两端的电容）和沟槽旁边的硅的耗尽电容来定义。 因此，电容器上的电压的增加会增加硅中的耗尽和耗尽电容，使得整体电容减小。 可以通过最小化可以通过确保与电容器相邻的硅尽可能高掺杂可以实现的耗尽区来抵消该效应。