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    Method for efficiently removing by-products produced in dry-etching
    1.
    发明授权
    Method for efficiently removing by-products produced in dry-etching 失效
    有效去除在干蚀刻中产生的副产物的方法

    公开(公告)号：US5674782A

    公开(公告)日：1997-10-07

    申请号：US611432

    申请日：1996-03-04

    申请人： Nae-in Lee ,  Moon-han Park ,  Young-wug Kim ,  Kwan-young Oh

    发明人： Nae-in Lee ,  Moon-han Park ,  Young-wug Kim ,  Kwan-young Oh

    IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/3213

    CPC分类号： H01L21/02071 ,  H01L21/28061 ,  H01L21/32135

    摘要： A method for efficiently removing by-products produced in dry-etching a fabricated structure of a semiconductor device, particularly, a polycide structure. The method includes the steps of sequentially forming a polysilicon layer and a refractory metal silicide layer to overlie previously fabricated structures on a semiconductor substrate, dry-etching the polysilicon layer and the refractory metal silicide layer to form a patterned polysilicon layer and a patterned refractory metal silicide layer, and thermal treating the resultant structure to remove at least one kind of by-product produced in the dry-etching step at a temperature higher than the boiling point of any by-product.

    摘要翻译： 一种用于有效地除去在干法蚀刻半导体器件，特别是多晶硅化物结构的制造结构中产生的副产物的方法。 该方法包括以下步骤：顺序地形成多晶硅层和难熔金属硅化物层以覆盖半导体衬底上先前制造的结构，干蚀刻多晶硅层和难熔金属硅化物层以形成图案化的多晶硅层和图案化的难熔金属 硅化物层，并对所得结构进行热处理，以在高于任何副产物的沸点的温度下除去在干蚀刻步骤中产生的至少一种副产物。

    Trench isolation regions having recess-inhibiting layers therein that protect against overetching
    2.
    发明授权
    Trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
    沟槽隔离区域在其中具有防止过蚀刻的凹陷抑制层

    公开(公告)号：US06717231B2

    公开(公告)日：2004-04-06

    申请号：US10224017

    申请日：2002-08-20

    申请人： Sung-eui Kim ,  Keum-joo Lee ,  In-seak Hwang ,  Young-sun Koh ,  Dong-ho Ahn ,  Moon-han Park ,  Tai-su Park

    发明人： Sung-eui Kim ,  Keum-joo Lee ,  In-seak Hwang ,  Young-sun Koh ,  Dong-ho Ahn ,  Moon-han Park ,  Tai-su Park

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.

    摘要翻译： 形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。 掩模层可以包括氮化硅。 然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。 接下来，在凹陷抑制层上形成应力消除层。 该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。 然后用沟槽隔离层填充沟槽。 然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。 使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。 凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。 以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。 还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

    Method for forming trench type isolation film using annealing
    3.
    发明授权
    Method for forming trench type isolation film using annealing 失效
    使用退火形成沟槽型隔离膜的方法

    公开(公告)号：US06624041B2

    公开(公告)日：2003-09-23

    申请号：US09316029

    申请日：1999-05-21

    申请人： Soo-jin Hong ,  Moon-han Park

    发明人： Soo-jin Hong ,  Moon-han Park

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224 ,  H01L21/823481

    摘要： A method for forming a trench type isolation film comprises filling a trench with a composite film, flattening the resultant, and annealing the flattened resultant before a gate oxide film is formed. The annealing diffuses out any contaminant existing in an area near and/or contacting the trench on a surface between a semiconductor substrate and a pad oxide film. Therefore, it is possible to prevent the portion of the gate oxide film which is near the trench from becoming thinner than other portions. Accordingly, it is possible to prevent the characteristic of the gate oxide film from deteriorating. In particular, it is possible to prevent a break down voltage from being lowered.

    摘要翻译： 用于形成沟槽型隔离膜的方法包括用复合膜填充沟槽，使所得的产品平坦化，并且在形成栅极氧化膜之前使扁平化的结果退火。 退火在半导体衬底和衬垫氧化物膜之间的表面上扩散存在于接近和/或接触沟槽的区域中的任何污染物。 因此，可以防止沟槽附近的栅极氧化膜的部分变得比其他部分薄。 因此，可以防止栅极氧化膜的特性劣化。 特别地，可以防止分解电压降低。

    Method of forming shallow trench isolation layer in semiconductor device
    4.
    发明授权
    Method of forming shallow trench isolation layer in semiconductor device 有权

    公开(公告)号：US06482715B2

    公开(公告)日：2002-11-19

    申请号：US09927340

    申请日：2001-08-13

    申请人： Tai-su Park ,  Ho-kyu Kang ,  Dong-ho Ahn ,  Moon-han Park

    发明人： Tai-su Park ,  Ho-kyu Kang ,  Dong-ho Ahn ,  Moon-han Park

    IPC分类号： H01L2176

    CPC分类号： H01L21/76229

    摘要： A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

    Isolation method of semiconductor device
    5.
    发明授权
    Isolation method of semiconductor device 失效
    半导体器件的隔离方法

    公开(公告)号：US5728620A

    公开(公告)日：1998-03-17

    申请号：US591826

    申请日：1996-01-25

    申请人： Moon-han Park

    发明人： Moon-han Park

    IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76224 ,  H01L21/76202

    摘要： A device isolation method divides a semiconductor substrate into active and inactive regions. A first device isolation layer is formed in a first inactive region using a trench isolation method. Then, local oxidation is used to form a second device isolation layer in a second inactive region which is wider than the first. A dishing phenomenon (generated during CMP processing) is eliminated, and proper device isolation is realized without exposing the active region.

    摘要翻译： 器件隔离方法将半导体衬底划分成活性和非活性区域。 使用沟槽隔离方法在第一非活性区域中形成第一器件隔离层。 然后，使用局部氧化在第二非活性区域中形成第二器件隔离层，其比第一非区域宽。 消除了凹陷现象（在CMP处理期间产生），并且在不暴露有源区的情况下实现适当的器件隔离。

    Methods of manufacturing semiconductor devices
    6.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US08877579B2

    公开(公告)日：2014-11-04

    申请号：US13417787

    申请日：2012-03-12

    申请人： Moon-kyun Song ,  Ha-jin Lim ,  Moon-han Park ,  Jin-ho Do

    发明人： Moon-kyun Song ,  Ha-jin Lim ,  Moon-han Park ,  Jin-ho Do

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8234

    CPC分类号： H01L21/823412 ,  H01L21/823807

    摘要： Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.

    摘要翻译： 制造半导体器件的方法包括提供包括NMOS区域和PMOS区域的衬底，将氟离子注入到衬底的上表面中，形成NMOS区域的第一栅极电极和衬底上的PMOS区域的第二栅极电极 在所述基板的与所述第一栅电极和所述第二栅电极的两个侧面相邻的部分分别形成源极区域和漏极区域，并在所述第一栅极电极和所述第二栅极电极的上表面上进行高压热处理工序 通过使用非氧化性气体的基板。

    MOS transistor with elevated source/drain structure
    9.
    发明授权
    MOS transistor with elevated source/drain structure 有权
    具有升高的源极/漏极结构的MOS晶体管

    公开(公告)号：US07368792B2

    公开(公告)日：2008-05-06

    申请号：US11388868

    申请日：2006-03-24

    申请人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

    发明人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

    摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

    摘要翻译： 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

    Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching
    10.
    发明授权
    Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
    形成其中具有防止过蚀刻的凹陷抑制层的沟槽隔离区的方法

    公开(公告)号：US06461937B1

    公开(公告)日：2002-10-08

    申请号：US09479442

    申请日：2000-01-07

    申请人： Sung-eui Kim ,  Keum-joo Lee ,  In-seak Hwang ,  Young-sun Koh ,  Dong-ho Ahn ,  Moon-han Park ,  Tai-su Park

    发明人： Sung-eui Kim ,  Keum-joo Lee ,  In-seak Hwang ,  Young-sun Koh ,  Dong-ho Ahn ,  Moon-han Park ,  Tai-su Park

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.

    摘要翻译： 形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。 掩模层可以包括氮化硅。 然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。 接下来，在凹陷抑制层上形成应力消除层。 该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。 然后用沟槽隔离层填充沟槽。 然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。 使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。 凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。 以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。 还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。