公开(公告)号：US07643347B2

公开(公告)日：2010-01-05

申请号：US12335093

申请日：2008-12-15

申请人： Naofumi Abiko ,  Masahiro Yoshihara

发明人： Naofumi Abiko ,  Masahiro Yoshihara

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C5/147 ,  G11C8/10 ,  G11C16/26 ,  G11C16/30

摘要： The semiconductor memory device related to an embodiment of the present invention including a memory string in which a plurality of memory cells are connected, a bit line connected to an end of the memory string, a power supply circuit which generates a voltage or a current related to an operation state of each memory cell, a sense amplifier which supplies a control voltage or a control current which controls an operation state of each memory cell via the bit line according to the voltage or the current generated in the power circuit, and a transient response adjustment circuit which adjusts the transient response characteristics of the voltage or the current generated in the power supply circuit when the sense amplifier supplies to the bit line the control voltage or the control current which shifts the memory string from a first operation state to a second operation state.

摘要翻译： 与本发明的实施例相关的半导体存储器件包括连接有多个存储单元的存储器串，连接到存储器串的端部的位线，产生电压或电流相关的电源电路 提供每个存储单元的操作状态，根据在电源电路中产生的电压或电流，通过位线提供控制电压或控制电流的读出放大器，其控制每个存储单元的操作状态，以及瞬态 响应调整电路，当感测放大器向位线提供控制电压或将存储器串从第一操作状态转移到第二操作状态的控制电流时，调整在电源电路中产生的电压或电流的瞬态响应特性 操作状态

公开(公告)号：US08923074B2

公开(公告)日：2014-12-30

申请号：US13432465

申请日：2012-03-28

申请人： Masahiro Yoshihara ,  Naofumi Abiko ,  Katsumi Abe

发明人： Masahiro Yoshihara ,  Naofumi Abiko ,  Katsumi Abe

IPC分类号： G11C7/10

CPC分类号： G11C7/1006 ,  G11C7/106 ,  G11C7/1087 ,  G11C16/0483 ,  G11C16/26

摘要： A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group including one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.

摘要翻译： 感测放大器电路连接到位线，并感测并放大从存储器单元读取的信号。 第一数据锁存器通过第一总线连接到读出放大器。 第二数据锁存器连接到第二总线。 多个电路组在第一方向上重复设置，每个电路组包括一个读出放大器电路和一个第一数据锁存器。 第二数据锁存器设置在电路组和输入/输出缓冲器之间。

公开(公告)号：US08009480B2

公开(公告)日：2011-08-30

申请号：US12630220

申请日：2009-12-03

申请人： Naofumi Abiko ,  Takuya Futatsuyama

发明人： Naofumi Abiko ,  Takuya Futatsuyama

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.

摘要翻译： 根据实施例，非易失性半导体存储器系统包括：非易失性半导体存储器; 以及存储器控制器，具有：存储器接口单元，其向非易失性半导体存储器输入命令并在非易失性半导体存储器之间输入或输出数据; 存储器，其存储表示在每个NAND单元单元中写入最新的存储单元晶体管的写入信息; 以及处理器，其基于写入信息设置读取电压，以从连接到第一字线的存储单元晶体管读出数据; 其中行控制器被配置为相对于用于识别存储在存储单元晶体管中的数据的一个阈值来设置要施加到第一字线的读取电压的多个电平。

公开(公告)号：US08363486B2

公开(公告)日：2013-01-29

申请号：US12884958

申请日：2010-09-17

申请人： Naofumi Abiko

发明人： Naofumi Abiko

IPC分类号： G11C7/10

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/26

摘要： According to one embodiment, in a nonvolatile semiconductor memory device, a data latch circuit which is connected to a sense amplifier circuit controls a data writing operation and a data reading operation to and from a nonvolatile memory cell array through a data bus, and outputs the stored data to the data bus when the sense amplifier circuit performs the data writing operation. The data latch circuit is provided with two nodes respectively storing and outputting normal data and reverse data which are connected to the data bus.

摘要翻译： 根据一个实施例，在非易失性半导体存储器件中，连接到读出放大器电路的数据锁存电路通过数据总线控制与非易失性存储单元阵列之间的数据写入操作和数据读取操作，并且输出 当读出放大器电路执行数据写入操作时，将数据存储到数据总线。 数据锁存电路设有两个节点，分别存储和输出连接到数据总线的正常数据和反向数据。

公开(公告)号：US20120250424A1

公开(公告)日：2012-10-04

申请号：US13432465

申请日：2012-03-28

申请人： Masahiro YOSHIHARA ,  Naofumi Abiko ,  Katsumi Abe

发明人： Masahiro YOSHIHARA ,  Naofumi Abiko ,  Katsumi Abe

IPC分类号： G11C7/06

CPC分类号： G11C7/1006 ,  G11C7/106 ,  G11C7/1087 ,  G11C16/0483 ,  G11C16/26

摘要： A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group comprising one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.

摘要翻译： 感测放大器电路连接到位线，并感测并放大从存储单元读取的信号。 第一数据锁存器通过第一总线连接到读出放大器。 第二数据锁存器连接到第二总线。 在第一方向重复提供多个电路组，每个电路组包括一个读出放大器电路和一个第一数据锁存器。 第二数据锁存器设置在电路组和输入/输出缓冲器之间。

公开(公告)号：US20120250409A1

公开(公告)日：2012-10-04

申请号：US13235430

申请日：2011-09-18

申请人： Hiroyuki KAGA ,  Masahiro Yoshihara ,  Naofumi Abiko

发明人： Hiroyuki KAGA ,  Masahiro Yoshihara ,  Naofumi Abiko

IPC分类号： G11C16/04

CPC分类号： G11C11/4096 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08

摘要： According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal.

摘要翻译： 根据一个实施例，半导体存储器包括存储单元阵列，存储单元阵列包括存储单元，存储单元沿着行方向和列方向排列，并且分别存储对应于阈值的数据，控制存储器行的行控制电路 单元阵列和列控制电路，其包括控制单元，所述控制单元根据与外部地址信号对应的指针，产生对应于存储单元阵列的列的控制元件的信号。

公开(公告)号：US08203885B2

公开(公告)日：2012-06-19

申请号：US13178718

申请日：2011-07-08

申请人： Naofumi Abiko ,  Takuya Futatsuyama

发明人： Naofumi Abiko ,  Takuya Futatsuyama

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.

摘要翻译： 根据实施例，非易失性半导体存储器系统包括：非易失性半导体存储器; 以及存储器控制器，具有：存储器接口单元，其向非易失性半导体存储器输入命令并在非易失性半导体存储器之间输入或输出数据; 存储器，其存储表示在每个NAND单元单元中写入最新的存储单元晶体管的写入信息; 以及处理器，其基于写入信息设置读取电压，以从连接到第一字线的存储单元晶体管读出数据; 其中行控制器被配置为相对于用于识别存储在存储单元晶体管中的数据的一个阈值来设置要施加到第一字线的读取电压的多个电平。

公开(公告)号：US08599613B2

公开(公告)日：2013-12-03

申请号：US13428914

申请日：2012-03-23

申请人： Naofumi Abiko ,  Masahiro Yoshihara

发明人： Naofumi Abiko ,  Masahiro Yoshihara

IPC分类号： G11C16/00

CPC分类号： G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C29/702

摘要： According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括存储单元阵列，其包括并行执行读和写的第一单元的存储单元，n（n是不少于2个的自然数）读出放大器，n个检测电路对应 配置成将从存储单元阵列读出的第一单位数据分割为z（z为自然数）第二单位数据的累加器，并累加第二单位数据写入不完整的故障位， 以及控制电路，被配置为控制在写入之后检测故障位的操作。

公开(公告)号：US08472248B2

公开(公告)日：2013-06-25

申请号：US13235430

申请日：2011-09-18

申请人： Hiroyuki Kaga ,  Masahiro Yoshihara ,  Naofumi Abiko

发明人： Hiroyuki Kaga ,  Masahiro Yoshihara ,  Naofumi Abiko

IPC分类号： G11C11/34

CPC分类号： G11C11/4096 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08

摘要： According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal.

摘要翻译： 根据一个实施例，半导体存储器包括存储单元阵列，存储单元阵列包括存储单元，存储单元沿着行方向和列方向排列，并且分别存储对应于阈值的数据，控制存储器行的行控制电路 单元阵列和列控制电路，其包括控制单元，所述控制单元根据与外部地址信号对应的指针，产生对应于存储单元阵列的列的控制元件的信号。

公开(公告)号：US20120002469A1

公开(公告)日：2012-01-05

申请号：US13051638

申请日：2011-03-18

申请人： Akihiro IMAMOTO ,  Naofumi Abiko

发明人： Akihiro IMAMOTO ,  Naofumi Abiko

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F11/1072 ,  G11C16/10 ,  G11C16/26

摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells selected by word lines and bit lines, each memory cell being capable of storing N-bit data, a set of n-th bits of a plurality of memory cells selected by one of the word lines constituting an n-th physical page, and a predetermined number of the bit lines constituting one column; and a data writing unit that divides each of first to N-th input data of the length of the physical page or less input from the outside into unit data of the length of the column, changes at least a portion of the order of unit data of the first to N-th input data of a predetermined column in the predetermined column before data writing, and performs writing.

摘要翻译： 根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括由字线和位线选择的多个存储单元，每个存储器单元能够存储N位数据，第n位的一组 由构成第n物理页的字线之一选择的多个存储单元和构成一列的预定数量的位线; 以及数据写入单元，其将物理页面的长度的第一至第N输入数据或从外部输入的输入数据分成列的长度的单位数据，改变单元数据的顺序的至少一部分 在数据写入之前的预定列中的预定列的第一至第N输入数据，并执行写入。