公开(公告)号：US20120063234A1

公开(公告)日：2012-03-15

申请号：US13226180

申请日：2011-09-06

申请人： Hitoshi SHIGA ,  Masahiro Yoshihara

发明人： Hitoshi SHIGA ,  Masahiro Yoshihara

IPC分类号： G11C16/10 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/30

摘要： According to one embodiment, a memory system includes a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory and a controller. The first memory has memory cells and executes a first operation that is at least one of write, read, and erase operations with respect to the memory cells. The first operation includes a first sub-operation and a second-sub operation that consume a current which is equal to or higher than a predetermined current. The second memory has memory cells and executes a second operation that is at least one of write, read, and erase operations with respect to the memory cells. The second operation includes a third sub-operation and a fourth sub-operation that consume a current which is equal to or higher than the predetermined current. The controller controls the first operation and the second operation of the first memory and the second memory.

摘要翻译： 根据一个实施例，存储器系统包括第一非易失性半导体存储器，第二非易失性半导体存储器和控制器。 第一存储器具有存储器单元并且执行与存储器单元相关的写入，读取和擦除操作中的至少一个的第一操作。 第一操作包括消耗等于或高于预定电流的电流的第一子操作和第二子操作。 第二存储器具有存储单元并且执行与存储单元相关的写入，读取和擦除操作中的至少一个的第二操作。 第二操作包括消耗等于或高于预定电流的电流的第三子操作和第四子操作。 控制器控制第一存储器和第二存储器的第一操作和第二操作。

公开(公告)号：US20110103152A1

公开(公告)日：2011-05-05

申请号：US13004926

申请日：2011-01-12

申请人： Masahiro YOSHIHARA ,  Toshiaki Edahiro ,  Koji Hosono

发明人： Masahiro YOSHIHARA ,  Toshiaki Edahiro ,  Koji Hosono

IPC分类号： G11C16/28

CPC分类号： G11C16/0483 ,  G11C7/065 ,  G11C7/067 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063 ,  G11C2207/068

摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.

摘要翻译： 半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。 感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管 以不通过第一和第二感测节点在位线中提供电流。

公开(公告)号：US20100226850A1

公开(公告)日：2010-09-09

申请号：US12160665

申请日：2007-01-19

申请人： Tadashi Ogasawara ,  Shinji Shimosaki ,  Kazuomi Azuma ,  Masahiro Yoshihara

发明人： Tadashi Ogasawara ,  Shinji Shimosaki ,  Kazuomi Azuma ,  Masahiro Yoshihara

IPC分类号： C01G23/04 ,  B05D3/02 ,  C23C16/08 ,  C25D11/26

CPC分类号： B01J35/004 ,  B01D53/8668 ,  B01D2255/20707 ,  B01D2255/802 ,  B01D2257/70 ,  B01D2259/804 ,  B01J21/063 ,  B01J37/0201 ,  B01J37/0215 ,  B01J37/0225 ,  B01J37/0244 ,  B01J37/03 ,  C01G23/0536 ,  C23C18/04 ,  C23C18/1204 ,  C23C18/1216 ,  C23C18/1241 ,  C23C18/1279 ,  C25D11/02 ,  C25D11/26

摘要： An even titanium oxide film is economically formed on the surface of a substrate. To actualize the film formation, an aqueous titanium tetrachloride solution containing 0.1 to 17% by weight of Ti is applied in a film-like state on the surface of a heat resistant substrate. While the liquid film state is kept as it is, the aqueous titanium tetrachloride solution is heated to 300° C. or more and H2O and HCl in the liquid film are accordingly evaporated to form a titanium oxide film. In the case where the substrate is of aluminum inferior in acid resistance, an acid-resistant film such as an oxide film is previously formed on the surface of the metal substrate.

摘要翻译： 在基板的表面上经济地形成均匀的氧化钛膜。 为了实现成膜，在耐热基材的表面上以薄膜状态涂布含有0.1〜17重量％Ti的四氯化钛水溶液。 在保持液膜状态的同时，将四氯化钛水溶液加热至300℃以上，从而蒸发液膜中的H 2 O和HCl，形成氧化钛膜。 在基板耐酸性差的情况下，在金属基板的表面上预先形成耐氧化膜如氧化膜。

公开(公告)号：US20100188913A1

公开(公告)日：2010-07-29

申请号：US12693798

申请日：2010-01-26

申请人： Masahiro YOSHIHARA ,  Katsumi ABE

发明人： Masahiro YOSHIHARA ,  Katsumi ABE

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C7/08 ,  G11C2207/005

摘要： A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell array, and includes a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page. The data line pair is arranged in the page buffer and is connected to the sense amplifiers. The differential amplifier is configured to amplify a potential difference between lines of the data line pair. The precharger is configured to precharge the data line pair to a predetermined potential. At least one of the differential amplifier and the precharger is formed in the page buffer, and the at least one circuit is electrically connected to the data line pair.

摘要翻译： 半导体存储器件包括存储单元阵列，页缓冲器，数据线对，差分放大器和预充电器。 存储单元阵列包括多个存储单元布置在其中的多个页面。 页面缓冲器形成在与存储单元阵列相邻的位置，并且包括多个读出放大器，被配置为临时保持从页面中的存储器单元读取的页面数据。 数据线对被布置在页缓冲器中并连接到读出放大器。 差分放大器被配置为放大数据线对的线之间的电位差。 预充电器被配置为将数据线对预充电到预定电位。 差分放大器和预充电器中的至少一个形成在页面缓冲器中，并且至少一个电路电连接到数据线对。

公开(公告)号：US20080225591A1

公开(公告)日：2008-09-18

申请号：US12043510

申请日：2008-03-06

申请人： Koji Hosono ,  Masahiro Yoshihara ,  Dai Nakamura ,  Youichi Kai

发明人： Koji Hosono ,  Masahiro Yoshihara ,  Dai Nakamura ,  Youichi Kai

IPC分类号： G11C16/06 ,  G11C5/14

CPC分类号： G11C16/30 ,  G11C5/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory according to an aspect of the invention includes memory cell arrays including plural cell units, a power supply pad disposed on one end in a first direction of the memory cell arrays, and page buffers disposed in the first direction of the memory cell arrays. The nonvolatile semiconductor memory also includes plural bit lines which are disposed on the memory cell arrays while extending in the first direction and a first power supply line which is disposed on the plural bit lines on the memory cell arrays to connect the power supply pad and the page buffers.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括存储单元阵列，其包括多个单元单元，设置在存储单元阵列的第一方向上的一端的电源垫，以及设置在存储单元的第一方向上的页缓冲器 阵列 非易失性半导体存储器还包括多个位线，它们沿着第一方向延伸设置在存储单元阵列上，第一电源线设置在存储单元阵列上的多个位线上，以将电源焊盘和 页面缓冲区。

公开(公告)号：US07177210B2

公开(公告)日：2007-02-13

申请号：US11363933

申请日：2006-03-01

申请人： Makoto Hamada ,  Kazuyoshi Muraoka ,  Masahiro Yoshihara

发明人： Makoto Hamada ,  Kazuyoshi Muraoka ,  Masahiro Yoshihara

IPC分类号： G11C11/00

CPC分类号： G11C29/027 ,  G11C29/02

摘要： A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.

摘要翻译： 半导体存储器包括具有备用存储单元阵列的存储单元阵列; 具有保险丝组的保持电路，被配置为读取和保持熔丝信息; 判定电路，被配置为基于来自保持电路的熔丝信息来确定存储器单元的哪个地址将被替换为哪个备用存储器单元; 以及保持控制器，被配置为通过接收电源完成信号和刷新信号来控制保持电路中的熔丝信息的读取和保持。 当保持电路通过接收供电完成信号一次读取熔丝信息之后，保持电路在产生再读信号时重新读取熔丝信息。

公开(公告)号：US20060279442A1

公开(公告)日：2006-12-14

申请号：US11438345

申请日：2006-05-23

申请人： Tohru Kimura ,  Masahiro Yoshihara ,  Masaru Koyanagi

发明人： Tohru Kimura ,  Masahiro Yoshihara ,  Masaru Koyanagi

IPC分类号： H03M1/10

CPC分类号： H03M1/1061 ,  G11C5/147 ,  G11C16/30 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A reference voltage generation circuit generates a reference voltage. An internal voltage generation circuit generates an internal voltage on the basis of the reference voltage generated by the reference voltage generation circuit. A first trimming circuit trims the internal voltage. During trimming of the internal voltage, the first trimming circuit trims an externally supplied first target voltage in accordance with first trimming data. The first trimming circuit ends the trimming when the first target voltage meets a given condition for the reference voltage.

摘要翻译： 参考电压产生电路产生参考电压。 内部电压产生电路基于由参考电压产生电路产生的参考电压产生内部电压。 第一个微调电路修剪内部电压。 在微调内部电压期间，第一微调电路根据第一微调数据修正外部提供的第一目标电压。 当第一目标电压满足参考电压的给定条件时，第一微调电路结束修整。

公开(公告)号：US07038969B2

公开(公告)日：2006-05-02

申请号：US10940635

申请日：2004-09-15

申请人： Makoto Hamada ,  Kazuyoshi Muraoka ,  Masahiro Yoshihara

发明人： Makoto Hamada ,  Kazuyoshi Muraoka ,  Masahiro Yoshihara

IPC分类号： G11C7/00

CPC分类号： G11C29/027 ,  G11C29/02

摘要： A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.

摘要翻译： 半导体存储器包括具有备用存储单元阵列的存储单元阵列; 具有保险丝组的保持电路，被配置为读取和保持熔丝信息; 判定电路，被配置为基于来自保持电路的熔丝信息来确定存储器单元的哪个地址将被替换为哪个备用存储器单元; 以及保持控制器，被配置为通过接收电源完成信号和刷新信号来控制保持电路中的熔丝信息的读取和保持。 当保持电路通过接收供电完成信号一次读取熔丝信息之后，保持电路在产生再读信号时重新读取熔丝信息。

公开(公告)号：US07035153B2

公开(公告)日：2006-04-25

申请号：US10978457

申请日：2004-11-02

申请人： Shintaro Hayashi ,  Manabu Satoh ,  Masahiro Yoshihara ,  Naoaki Kanagawa ,  Mami Kawabata

发明人： Shintaro Hayashi ,  Manabu Satoh ,  Masahiro Yoshihara ,  Naoaki Kanagawa ,  Mami Kawabata

IPC分类号： G11C29/00

CPC分类号： G11C29/816 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/4097

摘要： A semiconductor memory device adopting a bit line twist system in which at least a part of bit lines are twisted, includes memory cell arrays each having a plurality of memory cells to store data, redundancy cell arrays each having a plurality of redundancy cells to replace a defective cell in the memory cell array, and a control circuit which performs control to invert a direction of the data. The device further includes an inversion circuit which inverts the direction of the data, in accordance with the control by the control circuit.

摘要翻译： 采用位线扭转系统的半导体存储器件，其中位线的至少一部分被扭曲，包括每个具有多个存储单元以存储数据的存储单元阵列，每个具有多个冗余单元的冗余单元阵列以替代 存储单元阵列中的有缺陷的单元，以及执行用于反转数据的方向的控制的控制电路。 该装置还包括根据控制电路的控制来反转数据的方向的反相电路。

公开(公告)号：US20050088874A1

公开(公告)日：2005-04-28

申请号：US10940635

申请日：2004-09-15

申请人： Makoto Hamada ,  Kazuyoshi Muraoka ,  Masahiro Yoshihara

发明人： Makoto Hamada ,  Kazuyoshi Muraoka ,  Masahiro Yoshihara

IPC分类号： G11C11/413 ,  G11C29/02 ,  G11C29/04 ,  G11C17/00

CPC分类号： G11C29/027 ,  G11C29/02

摘要： A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on the fuse information from the holding circuit; and a holding-controller configured to control reading and holding of the fuse information in the holding circuit by receiving a power supply completion signal and a refresh signal. The holding circuit rereads the fuse information when the reread signal is generated, after the holding circuit reads once the fuse information by receiving the power supplying completion signal.

摘要翻译： 半导体存储器包括具有备用存储单元阵列的存储单元阵列; 具有保险丝组的保持电路，被配置为读取和保持熔丝信息; 判定电路，被配置为基于来自保持电路的熔丝信息来确定存储器单元的哪个地址将被替换为哪个备用存储器单元; 以及保持控制器，被配置为通过接收电源完成信号和刷新信号来控制保持电路中的熔丝信息的读取和保持。 当保持电路通过接收供电完成信号一次读取熔丝信息之后，保持电路在产生再读信号时重新读取熔丝信息。