公开(公告)号：US07759744B2

公开(公告)日：2010-07-20

申请号：US11129440

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62 ,  H01L27/10 ,  H01L29/73

CPC分类号： H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.

摘要翻译： 半导体器件100包括硅衬底102，在硅衬底102上包括第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数膜的P型MOSFET 120 12和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。第一 高介电常数膜111和第二高介电常数膜112含有选自Hf和Zr的一种或多种元素。

公开(公告)号：US20050253181A1

公开(公告)日：2005-11-17

申请号：US11129440

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L31/119

CPC分类号： H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 formed on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 112 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from a group consisting of Hf and Zr.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数的P型MOSFET 120 膜112和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。 第一高介电常数膜111和第二高介电常数膜112包含从由Hf和Zr组成的组中选择的一种或多种元素。

公开(公告)号：US20120195100A1

公开(公告)日：2012-08-02

申请号：US13359449

申请日：2012-01-26

申请人： Motofumi SAITOH ,  Masayuki Terai

发明人： Motofumi SAITOH ,  Masayuki Terai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/145

摘要： Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.

摘要翻译： 提供一种半导体器件，包括：具有可变电阻器件的存储单元; 以及控制单元，其控制施加到所述存储单元的电压，其中所述可变电阻装置包括下电极，所述下电极包含第一金属材料，包含第二金属材料的上电极和含氧的绝缘膜，所述第一金属材料具有 归一化的氧化物形成能量高于第二金属材料，并且控制单元在增加绝缘膜的电阻值的操作时向上部电极施加正电压，并且降低其电阻值的操作 并且在读出绝缘膜的电阻值的操作时向下电极施加正电压。

公开(公告)号：US08787067B2

公开(公告)日：2014-07-22

申请号：US13359449

申请日：2012-01-26

申请人： Motofumi Saitoh ,  Masayuki Terai

发明人： Motofumi Saitoh ,  Masayuki Terai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/145

摘要： Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film.

摘要翻译： 提供一种半导体器件，包括：具有可变电阻器件的存储单元; 以及控制单元，其控制施加到所述存储单元的电压，其中所述可变电阻装置包括下电极，所述下电极包含第一金属材料，包含第二金属材料的上电极和含氧的绝缘膜，所述第一金属材料具有 归一化的氧化物形成能量高于第二金属材料，并且控制单元在增加绝缘膜的电阻值的操作时向上部电极施加正电压，并且降低其电阻值的操作 并且在读出绝缘膜的电阻值的操作时向下电极施加正电压。

公开(公告)号：US08692309B2

公开(公告)日：2014-04-08

申请号：US13559859

申请日：2012-07-27

申请人： Masayuki Terai

发明人： Masayuki Terai

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L29/42344 ,  H01L29/792

摘要： In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 1 a first gate lamination structure which comprises a first insulating film 11 including a trap layer, and a first conductive body 9, and a second gate lamination structure which comprises a second insulating film 12 free of a trap layer and including an insulating film layer 13 doped with metal for controlling the work function at least on the upper layer, and a second conductive body 10. A source drain region 2 and a source drain region 3 are formed such that the first gate lamination structure and the second gate lamination structure are interleaved therebetween.The effective work function of the second gate lamination structure is higher than that of the first gate lamination structure.

摘要翻译： 在陷阱型存储芯片中，耐压升高，然后读出电流增加。 在p型半导体衬底1上形成第一栅极层压结构，其包括具有陷阱层的第一绝缘膜11和第一导电体9以及第二栅极层叠结构，该第二栅极叠层结构包括第二绝缘膜12， 陷阱层，并且包括掺杂有用于至少在上层上控制功函数的金属的绝缘膜层13和第二导电体10.源漏极区域2和源极漏极区域3形成为使得第一栅极 层压结构和第二栅极层压结构之间交错。 第二栅极层叠结构的有效功函数高于第一栅极层叠结构的功函数。

公开(公告)号：US08148757B2

公开(公告)日：2012-04-03

申请号：US12447113

申请日：2007-10-23

申请人： Masayuki Terai ,  Shinji Fujieda ,  Akio Toda

发明人： Masayuki Terai ,  Shinji Fujieda ,  Akio Toda

IPC分类号： H01L29/04 ,  H01L29/92

CPC分类号： H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/7923 ,  H01L29/7926

摘要： A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

摘要翻译： 在基板的凹部或突出部形成沟道，并且形成栅极绝缘膜，以沿着沟道具有第一至第三绝缘区域。 第一绝缘区域和第三绝缘区域的每个栅极绝缘膜具有不包含形成在不同于基板的主面的平面上的电荷阱的第一栅极绝缘膜，含有电荷阱的电荷积累膜，以及 不含电荷陷阱的第二栅绝缘膜。 中间的第二绝缘区域的栅极绝缘膜形成在与基板的主表面平行的平面上，并且仅由不含电荷陷阱的第三栅极绝缘膜构成。

公开(公告)号：US07821823B2

公开(公告)日：2010-10-26

申请号：US12095866

申请日：2006-12-01

申请人： Hiroshi Sunamura ,  Kouji Masuzaki ,  Masayuki Terai

发明人： Hiroshi Sunamura ,  Kouji Masuzaki ,  Masayuki Terai

IPC分类号： G11C16/04

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/792

摘要： Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.

摘要翻译： 公开了一种半导体存储装置，包括半导体衬底，形成在半导体衬底中的第一和第二杂质扩散层，形成在半导体衬底上的栅极绝缘膜，以及通过栅极绝缘膜形成在半导体衬底上的第一栅电极 。 栅极绝缘膜在内部具有含氮氧化硅膜，并且在含氮氧化硅膜的两侧配置氧化硅膜以夹持含氮氧化硅膜。 此外，含氮氧化硅膜中的氮组成从半导体衬底侧增加到第一栅电极侧。

公开(公告)号：US20130077379A1

公开(公告)日：2013-03-28

申请号：US13553764

申请日：2012-07-19

申请人： Masaharu Matsudaira ,  Masayuki Terai

发明人： Masaharu Matsudaira ,  Masayuki Terai

IPC分类号： H01L47/00 ,  H01L21/02 ,  G11C11/00

CPC分类号： H01L27/10852 ,  H01L27/101 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/2436 ,  H01L28/91 ,  H01L45/04 ,  H01L45/146 ,  H01L45/1683

摘要： In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

摘要翻译： 在将DRAM和ReRAM安装在一起的情况下，其制造成本降低，同时保持电容元件和可变电阻元件的性能。 半导体存储器件包括可变电阻元件和电容元件。 可变电阻元件具有具有第一深度的圆筒型MIM结构，并且被设计用于可变电阻型存储器。 电容元件具有比第一深度更深的第二深度的圆筒型MIM结构，并且被设计用于DRAM。

公开(公告)号：US20100090257A1

公开(公告)日：2010-04-15

申请号：US12447113

申请日：2007-10-23

申请人： Masayuki Terai ,  Shinji Fujieda ,  Akio Toda

发明人： Masayuki Terai ,  Shinji Fujieda ,  Akio Toda

IPC分类号： H01L29/04 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/7923 ,  H01L29/7926

摘要： A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

摘要翻译： 在基板的凹部或突出部形成沟道，并且形成栅极绝缘膜，以沿着沟道具有第一至第三绝缘区域。 第一绝缘区域和第三绝缘区域的每个栅极绝缘膜具有不包含形成在不同于基板的主面的平面上的电荷阱的第一栅极绝缘膜，含有电荷阱的电荷积累膜，以及 不含电荷陷阱的第二栅绝缘膜。 中间的第二绝缘区域的栅极绝缘膜形成在与基板的主表面平行的平面上，并且仅由不含电荷陷阱的第三栅极绝缘膜构成。

公开(公告)号：US20100025755A1

公开(公告)日：2010-02-04

申请号：US12519685

申请日：2007-12-17

申请人： Masayuki Terai

发明人： Masayuki Terai

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L29/42344 ,  H01L29/792

摘要： In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 1 a first gate lamination structure which comprises a first insulating film 11 including a trap layer, and a first conductive body 9, and a second gate lamination structure which comprises a second insulating film 12 free of a trap layer and including an insulating film layer 13 doped with metal for controlling the work function at least on the upper layer, and a second conductive body 10. A source drain region 2 and a source drain region 3 are formed such that the first gate lamination structure and the second gate lamination structure are interleaved therebetween. The effective work function of the second gate lamination structure is higher than that of the first gate lamination structure.

摘要翻译： 在陷阱型存储芯片中，耐压升高，然后读出电流增加。 在p型半导体衬底1上形成第一栅极层压结构，其包括具有陷阱层的第一绝缘膜11和第一导电体9以及第二栅极层叠结构，该第二栅极叠层结构包括第二绝缘膜12， 陷阱层，并且包括掺杂有用于至少在上层上控制功函数的金属的绝缘膜层13和第二导电体10.源漏极区域2和源极漏极区域3形成为使得第一栅极 层压结构和第二栅极层压结构之间交错。 第二栅极层叠结构的有效功函数高于第一栅极层叠结构的功函数。