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1.发明授权公开(公告)号：US07725694B2
公开(公告)日：2010-05-25
申请号：US11312830
申请日：2005-12-21
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3842 , G06F9/3861
摘要： A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.
摘要翻译： 微型计算机包括能够在并行分时操作中执行多个任务的CPU。 这些任务包括至少一个具有固定循环程序的特殊任务，其具有指令地址的不断增加。 当CPU在特殊任务中执行条件判断指令时，CPU在不需要执行特殊操作中描述的指令的情况下禁止将CPU和外围电路两者的条件判断指令的执行结果反映 条件判决指示后的任务。
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2.发明申请公开(公告)号：US20060155976A1
公开(公告)日：2006-07-13
申请号：US11312830
申请日：2005-12-21
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/3842 , G06F9/3861
摘要： A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgement instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgement instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgement instruction.
摘要翻译： 微型计算机包括能够在并行分时操作中执行多个任务的CPU。 这些任务包括至少一个具有固定循环程序的特殊任务，其具有指令地址的不断增加。 当CPU在特殊任务中执行条件判断指令时，CPU在不需要执行特殊操作中描述的指令的情况下禁止将CPU和外围电路两者的条件判断指令的执行结果反映 条件判决指示后的任务。
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公开(公告)号：US20090009211A1
公开(公告)日：2009-01-08
申请号：US12155017
申请日：2008-05-29
IPC分类号： H03K19/00
CPC分类号： G06F11/26
摘要： A microcomputer for functioning according to operation modes includes: a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.
摘要翻译： 根据操作模式起作用的微计算机包括：对施加到模式设置终端的信号中的电平变化次数进行计数的模式计数器; 解码模式计数器的输出数据以输出表示一种操作模式的模式信号的模式解码器; 时钟输入端子; 数据终端，串行数据与施加到时钟输入端的串行时钟信号同步输入; 串行到并行转换单元，将串行数据转换为并行数据，并将并行数据存储在输入数据缓冲器中; 以及切换装置，切换到CPU能够以测试模式访问输入数据缓冲器的状态。 在测试模式下，能够从外部电路输入测试指令数据。
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4.发明授权Microcomputer with mode decoder operable upon receipt of either power-on or external reset signal 有权具有模式解码器的微计算机，在接收到电源接通或外部复位信号时可操作公开(公告)号：US07467294B2
公开(公告)日：2008-12-16
申请号：US11270447
申请日：2005-11-10
IPC分类号： G06F9/00
CPC分类号： G06F1/24
摘要： A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.
摘要翻译： 微型计算机包括多个操作模式选择端子，用于选择多个操作模式的数据。 多个操作模式选择端子被设计为可用作通用输入端子或输出端子。 解码器将对多个操作模式选择端子设置的数据进行解码，并根据选择的操作模式输出用于切换内部功能的模式信号。 定时信号输出单元向解码器输出用于使解码器执行解码操作的定时信号。 当上电复位和外部控制的复位中的至少一个从活动状态变为非活动状态时，定时信号输出单元输出定时信号。
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公开(公告)号：US20060107082A1
公开(公告)日：2006-05-18
申请号：US11270447
申请日：2005-11-10
IPC分类号： G06F1/30
CPC分类号： G06F1/24
摘要： A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.
摘要翻译： 微型计算机包括多个操作模式选择端子，用于选择多个操作模式的数据。 多个操作模式选择端子被设计为可用作通用输入端子或输出端子。 解码器将对多个操作模式选择端子设置的数据进行解码，并根据选择的操作模式输出用于切换内部功能的模式信号。 定时信号输出单元向解码器输出用于使解码器执行解码操作的定时信号。 当上电复位和外部控制的复位中的至少一个从活动状态变为非活动状态时，定时信号输出单元输出定时信号。
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公开(公告)号：US07890737B2
公开(公告)日：2011-02-15
申请号：US12155017
申请日：2008-05-29
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： A microcomputer for functioning according to operation modes includes; a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.
摘要翻译： 根据操作模式起作用的微型计算机包括： 模式计数器，其对施加到模式设置终端的信号中的电平变化次数进行计数; 解码模式计数器的输出数据以输出表示一种操作模式的模式信号的模式解码器; 时钟输入端子; 数据终端，串行数据与施加到时钟输入端的串行时钟信号同步输入; 串行到并行转换单元，将串行数据转换为并行数据，并将并行数据存储在输入数据缓冲器中; 以及切换装置，切换到CPU能够以测试模式访问输入数据缓冲器的状态。 在测试模式下，能够从外部电路输入测试指令数据。
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7.发明授权Semiconductor integrated circuit device and microcomputer development supporting device 失效半导体集成电路器件和微机开发支持器件公开(公告)号：US07421384B2
公开(公告)日：2008-09-02
申请号：US11000902
申请日：2004-12-02
申请人： Kenji Yamada , Hideaki Ishihara , Kyouichi Suzuki , Yoshinori Teshima , Toshihiko Matsuoka , Naoki Ito
发明人： Kenji Yamada , Hideaki Ishihara , Kyouichi Suzuki , Yoshinori Teshima , Toshihiko Matsuoka , Naoki Ito
IPC分类号： G06F9/455 , G06F11/00 , G06F15/00 , G06F15/76 , G06F19/00 , G01R31/28 , G01R27/28 , G01R31/00 , G01R31/14
CPC分类号： G06F11/261
摘要： During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.
摘要翻译： 在软件开发过程中，使用一个多芯片模块，将一个目标芯片和一个开发芯片封装在一个封装中。 开发芯片的CPU从芯片中的闪速存储器中获取指令以执行它们，并访问芯片中的RAM和外围电路。 对于仅在目标芯片中存在的电机控制电路，CPU通过串行通信访问它们。 当单片机单独运行时，其CPU将开关电路切换到JTAG接口侧，以通过内部串行通信来驱动电机控制电路。
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8.发明申请Semiconductor integrated circuit device and microcomputer development supporting device 失效半导体集成电路器件和微机开发支持器件公开(公告)号：US20050125214A1
公开(公告)日：2005-06-09
申请号：US11000902
申请日：2004-12-02
申请人： Kenji Yamada , Hideaki Ishihara , Kyouichi Suzuki , Yoshinori Teshima , Toshihiko Matsuoka , Naoki Ito
发明人： Kenji Yamada , Hideaki Ishihara , Kyouichi Suzuki , Yoshinori Teshima , Toshihiko Matsuoka , Naoki Ito
CPC分类号： G06F11/261
摘要： During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.
摘要翻译： 在软件开发过程中，使用一个多芯片模块，将一个目标芯片和一个开发芯片封装在一个封装中。 开发芯片的CPU从芯片中的闪速存储器中获取指令以执行它们，并访问芯片中的RAM和外围电路。 对于仅在目标芯片中存在的电机控制电路，CPU通过串行通信访问它们。 当单片机单独运行时，其CPU将开关电路切换到JTAG接口侧，以通过内部串行通信来驱动电机控制电路。
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公开(公告)号：US07444529B2
公开(公告)日：2008-10-28
申请号：US11238106
申请日：2005-09-29
IPC分类号： G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/128
摘要： A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or interrupts or resumes the supply of an external power source in response to resumption of the halted operation. When the CPU is to be shifted to the sleep mode, the frequency multiplier circuit holds the set oscillation control conditions. When the oscillating operation is to be resumed, operates based on the oscillation control conditions that are held. When the sleep mode is reset, the CPU makes access to the mask ROM and immediately reads out a control program that is to be executed right after the wakeup.
摘要翻译： CPU在转移到休眠模式时，通过低功耗控制电路中止振荡电路和倍频器电路的振荡操作。 闪光电源电路中断电路或中断的振荡操作或响应于恢复停止的操作来恢复外部电源的供应。 当CPU被切换到睡眠模式时，倍频电路保持设定的振荡控制条件。 当振荡操作要恢复时，基于所保持的振荡控制条件进行操作。 当睡眠模式复位时，CPU访问掩码ROM，并立即读出在唤醒之后要执行的控制程序。
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公开(公告)号：US20060069933A1
公开(公告)日：2006-03-30
申请号：US11238106
申请日：2005-09-29
IPC分类号： G06F1/26
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/128
摘要： A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or interrupts or resumes the supply of an external power source in response to resumption of the halted operation. When the CPU is to be shifted to the sleep mode, the frequency multiplier circuit holds the set oscillation control conditions. When the oscillating operation is to be resumed, operates based on the oscillation control conditions that are held. When the sleep mode is reset, the CPU makes access to the mask ROM and immediately reads out a control program that is to be executed right after the wakeup.
摘要翻译： CPU在转移到休眠模式时，通过低功耗控制电路中止振荡电路和倍频器电路的振荡操作。 闪光电源电路中断电路或中断的振荡操作或响应于恢复停止的操作来恢复外部电源的供应。 当CPU被切换到睡眠模式时，倍频电路保持设定的振荡控制条件。 当振荡操作要恢复时，基于所保持的振荡控制条件进行操作。 当睡眠模式复位时，CPU访问掩码ROM，并立即读出在唤醒之后要执行的控制程序。
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