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36 条记录 (耗时 0.032 秒)

    Integrate and fold analog-to-digital converter with saturation prevention
    1.
    发明授权
    Integrate and fold analog-to-digital converter with saturation prevention 失效
    集成和折叠具有饱和度预防的模数转换器

    公开(公告)号：US06366231B1

    公开(公告)日：2002-04-02

    申请号：US09546623

    申请日：2000-04-10

    申请人： Naresh Kesavan Rao ,  Daniel David Harrison ,  Donald Thomas McGrath ,  Jerome Johnson Tiemann

    发明人： Naresh Kesavan Rao ,  Daniel David Harrison ,  Donald Thomas McGrath ,  Jerome Johnson Tiemann

    IPC分类号： H03M150

    CPC分类号： H03M1/141 ,  H03M1/1215 ,  H03M1/60

    摘要： An analog to digital conversion circuit for converting an analog input signal into a plurality of binary output bits includes an operational amplifier and an integrating capacitor for storing a charge proportional to the integral of the input signal. A charge subtracting circuit removes a first predetermined charge from the integrating capacitor when an output charge of the operational amplifier is substantially equal to a second predetermined charge. The first predetermined charge level is removed from the integrating capacitor a number of times. The removal of the first predetermined charge from the integrating capacitor allows the integral of the analog input signal to be larger than a maximum charge capable of being stored by the integrating capacitor. A digital logic circuit tracks the number of times that the first predetermined charge is removed from the integrating capacitor by the charge subtracting circuit, and the digital logic circuit provides at least one bit of the plurality of binary output bits. A residue quantizing circuit determines a residual charge in the integrating capacitor and provides at least one additional bit of the plurality of binary output bits corresponding to the residual charge. The residual charge is substantially equal to a stored charge in the integrating capacitor after the first predetermined charge has been removed the number of times.

    摘要翻译： 用于将模拟输入信号转换成多个二进制输出位的模数转换电路包括运算放大器和用于存储与输入信号的积分成比例的电荷的积分电容器。 当运算放大器的输出电荷基本上等于第二预定电荷时，电荷减去电路从积分电容器去除第一预定电荷。 第一预定电荷电平从积分电容器中多次去除。 从积分电容器去除第一预定电荷允许模拟输入信号的积分大于能够由积分电容器存储的最大电荷。 数字逻辑电路跟踪由电荷减法电路从积分电容器去除第一预定电荷的次数，数字逻辑电路提供多个二进制输出位的至少一位。 残余量化电路确定积分电容器中的残余电荷，并提供与剩余电荷相对应的多个二进制输出位中的至少一个附加位。 残余电荷基本上等于在第一预定电荷已被去除次数之后积分电容器中的存储电荷。

    Low power signal processing for spread spectrum receivers
    9.
    发明授权
    Low power signal processing for spread spectrum receivers 失效
    用于扩频接收机的低功率信号处理

    公开(公告)号：US6028883A

    公开(公告)日：2000-02-22

    申请号：US883162

    申请日：1997-06-26

    申请人： Jerome Johnson Tiemann ,  Daniel David Harrison

    发明人： Jerome Johnson Tiemann ,  Daniel David Harrison

    IPC分类号： G01S1/00 ,  G01S5/00 ,  G01S5/14 ,  G01S19/24 ,  G01S19/37 ,  G06F17/15 ,  H04B1/16 ,  H04B1/707 ,  H04B1/708 ,  H04B1/709 ,  H04B1/7107 ,  H04B15/00

    CPC分类号： H04B1/708 ,  G01S19/09 ,  G01S19/29 ,  G01S19/30 ,  G01S19/34 ,  G01S19/37 ,  G01S5/0027 ,  G01S5/0036 ,  G06F17/15 ,  H04B1/707 ,  H04B1/709 ,  H04B1/71075 ,  G01S19/42 ,  G01S5/0054 ,  H04B2201/70709 ,  H04W52/0283

    摘要： A direct sequence spread spectrum architecture permits low power consumption during a synchronization phase of data reception by allowing the receiver to be turned off during most of the acquisition phase of reception, or by using a parallel correlator to keep acquisition time short. The architecture is particularly suitable for global positioning satellite (GPS) signal processing and permits multiple satellite codes and multiple Doppler bins to be searched either sequentially, without requiring the receiver to be turned on during the search process. The receiver output baseband data is sampled and stored over a time interval sufficient to achieve acquisition and synchronization for any one code division multiple access (CDMA) signal at any specific Doppler shift. This sample is digitally recorded and re-played from memory as many times as may be required to acquire and synchronize each desired CDMA signal. To keep processing energy consumption low, an analog (capacitor-based) cross-correlator is used. The order of coherent and non-coherent processing for all code-Doppler channels is chosen to maximize energy efficiency while minimizing required processor hardware.

    摘要翻译： 直接序列扩展频谱架构允许在数据接收的同步阶段期间通过允许接收机在接收的大部分接收阶段期间关闭接收机，或通过使用并行相关器来保持采集时间短的低功耗。 该架构特别适用于全球定位卫星（GPS）信号处理，并允许依次搜索多个卫星码和多个多普勒频段，而不需要在搜索过程中接收接收机。 接收机输出基带数据被采样并存储在足以实现任何特定多普勒频移处的任何一个码分多址（CDMA）信号的采集和同​​步的时间间隔。 该采样数据记录并从存储器再次播放，可能需要多次以获得并同步每个期望的CDMA信号。 为了保持处理能耗低，使用了模拟（基于电容器的）互相关器。 选择所有代码多普勒通道的相干和非相干处理的顺序，以最大限度地提高能源效率，同时最小化所需的处理器硬件。

    Parallel correlator for a spread spectrum receiver
    10.
    发明授权
    Parallel correlator for a spread spectrum receiver 失效
    用于扩频接收机的并行相关器

    公开(公告)号：US6009118A

    公开(公告)日：1999-12-28

    申请号：US883163

    申请日：1997-06-26

    申请人： Jerome Johnson Tiemann ,  Daniel David Harrison

    发明人： Jerome Johnson Tiemann ,  Daniel David Harrison

    IPC分类号： G01S1/00 ,  G01S5/00 ,  G01S5/14 ,  G01S19/24 ,  G01S19/37 ,  G06F17/15 ,  H04B1/16 ,  H04B1/708 ,  H04B1/709 ,  H04B1/7107 ,  H04B1/707

    CPC分类号： H04B1/708 ,  G01S19/09 ,  G01S19/29 ,  G01S19/30 ,  G01S19/34 ,  G01S19/37 ,  G01S5/0027 ,  G01S5/0036 ,  G06F17/15 ,  H04B1/709 ,  H04B1/71075 ,  G01S19/42 ,  G01S5/0054 ,  H04B2201/70709 ,  H04W52/0283

    摘要： A direct sequence spread spectrum receiver samples an incoming signal and stores the sample in memory. The signal sample is read from memory as necessary to process the signal without further signal acquisition. The correlator calculates an inner product by simultaneously correlating each bit of the sample with a corresponding bit of a replica signal. If the inner product does not exceed a threshold value the correlator calculates another inner product between the same signal sample and another replica signal. This occurs until all available signals are identified. In one embodiment, memory is segmented and each segment is read by a separate correlator allowing faster identification of one signal or multiple signals to be acquired simultaneously. Such a receiver is useful in global positioning satellite (GPS) signal processing where the incoming signal contains several satellite transmissions encoded with CDMA encoding.

    摘要翻译： 直接序列扩频接收机对输入信号进行采样并将样本存储在存储器中。 根据需要从存储器读取信号样本，以处理信号而无需进一步的信号采集。 相关器通过将样本的每个位与副本信号的相应位同时相关来计算内积。 如果内积不超过阈值，则相关器计算相同信号样本与另一副本信号之间的另一内积。 直到所有可用的信号被识别才发生。 在一个实施例中，存储器被分段，并且每个段由单独的相关器读取，允许更快地识别要同时获取的一个信号或多个信号。 这样的接收机在全球定位卫星（GPS）信号处理中是有用的，其中输入信号包含用CDMA编码编码的几个卫星传输。