公开(公告)号：US20070266284A1

公开(公告)日：2007-11-15

申请号：US11380677

申请日：2006-04-28

申请人： Nathan Chelstrom ,  Steven Ferguson ,  Mack Riley

发明人： Nathan Chelstrom ,  Steven Ferguson ,  Mack Riley

IPC分类号： G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/318558

摘要： A system and method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device. With the system and method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

摘要翻译： 一种用于在集成电路设备的异步时钟边界处测试功能边界逻辑的系统和方法。 使用系统和方法，每个时钟域都有自己的扫描路径，不会跨域的边界。 通过消除跨越边界的扫描，可以消除在异步计时域中具有两个时钟网格的要求。 结果，电路面积和时钟分配设计的设计时间缩短了。 此外，在异步计时域中去除第二时钟网格，即高速核心或系统时钟，消除了在异步域中选择时钟信号的复用方案的要求。 除了上述之外，系统和方法还提供了边界内置的自检逻辑，用于在功能操作模式下测试时钟域之间边界的功能交叉逻辑。

公开(公告)号：US20070130489A1

公开(公告)日：2007-06-07

申请号：US11295057

申请日：2005-12-06

申请人： Naoki Kiryu ,  Mack Riley ,  Nathan Chelstrom

发明人： Naoki Kiryu ,  Mack Riley ,  Nathan Chelstrom

IPC分类号： G01R31/28

CPC分类号： G01R31/318536

摘要： Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed to determine whether any of the processor cores is malfunctioning. If none of the processor cores malfunctions, the processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor is fully functional. If one or more processor cores malfunctions, these processor cores are isolated and the remaining processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor operates properly with reduced functionality.

摘要翻译： 用于在数字电路中执行逻辑内置自检（LBIST）的系统和方法，其中电路功能块中的边界扫描链可以选择性耦合/去耦以在LBIST测试期间隔离功能块。 在一个实施例中，多处理器芯片的处理器核是隔离的，并且执行LBIST测试以确定任何处理器核心是否发生故障。 如果没有处理器内核发生故障，处理器内核将与设备的支持功能块一起进行测试，以确定多处理器是否完全正常工作。 如果一个或多个处理器内核发生故障，则这些处理器内核是隔离的，剩余的处理器内核将与设备的支持功能块一起进行测试，以确定多处理器是否以降低的功能正常运行。

公开(公告)号：US20070168688A1

公开(公告)日：2007-07-19

申请号：US11242674

申请日：2005-10-04

申请人： Nathan Chelstrom ,  Mack Riley ,  Shoji Sawamura

发明人： Nathan Chelstrom ,  Mack Riley ,  Shoji Sawamura

IPC分类号： G06F1/04 ,  G06F1/24

CPC分类号： G06F1/04 ,  G06F11/3632

摘要： A clock control hierarchy is provided that is comprised of synchronous and asynchronous hold request signals that are used to start and stop functional units of a chip. Pervasive logic is provided that uses a synchronous “chip hold” signal and asynchronous latch/functional unit hold signals to individually target functional units and latches that are to remain in a held state once the “chip hold” state is released. With the present invention, a chip hold request is first activated followed by scannable latch and non-scannable latch hold requests being activated to identify which latches will be clocked or not clocked when the chip hold is released. Functional unit hold signals are activated to place certain ones of the functional units of the chip in a hold state. The chip hold request is deactivated and the chip operates with the selected functional units and latches being maintained in a held state.

摘要翻译： 提供了一种时钟控制层级，其包括用于启动和停止芯片的功能单元的同步和异步保持请求信号。 提供了普遍的逻辑，其使用同步的“芯片保持”信号和异步锁存/功能单元保持信号来单独地定位一旦释放“芯片保持”状态将保持在保持状态的功能单元和锁存器。 利用本发明，芯片保持请求首先被激活，随后是可扫描锁存器，并且不可扫描的锁存保持请求被激活以识别当芯片保持被释放时哪些锁存器将被计时或不被计时。 激活功能单元保持信号以将芯片中的某些功能单元置于保持状态。 芯片保持请求被禁用，并且芯片操作，所选功能单元和锁存器保持在保持状态。

公开(公告)号：US20070081620A1

公开(公告)日：2007-04-12

申请号：US11245308

申请日：2005-10-06

申请人： Irene Beattie ,  Nathan Chelstrom ,  Matthew Fernsler ,  Mack Riley

发明人： Irene Beattie ,  Nathan Chelstrom ,  Matthew Fernsler ,  Mack Riley

IPC分类号： H03D3/24

CPC分类号： H03L7/06 ,  H03L7/10

摘要： An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.

摘要翻译： 提供了使用电熔丝（eFuses）来存储锁相环（PLL）配置数据的装置和方法。 利用该装置和方法，集成电路中存在的eFus的一部分被保留用于PLL配置数据。 上电时，上电控制器和eFuse控制器将eFuse部分中的数据的感测和串行传输指引到参考时钟下的PLL。 传输完成后，上电控制器指示PLL逻辑来加载配置数据并启动。 本发明的机构允许制造基于该设备的特性及其预期用途来定制给定设备上的PLL配置。 因此，可以在相同或不同的架构中使用相同的PLL，以便根据从eFuses传入PLL的配置数据执行不同的操作。

公开(公告)号：US20070168809A1

公开(公告)日：2007-07-19

申请号：US11199972

申请日：2005-08-09

申请人： Naoki Kiryu ,  Nathan Chelstrom ,  Mack Riley ,  Louis Bushard

发明人： Naoki Kiryu ,  Nathan Chelstrom ,  Mack Riley ,  Louis Bushard

IPC分类号： G01R31/28

CPC分类号： G01R31/3187 ,  G01R31/31724 ,  G01R31/318563

摘要： Systems and methods for performing logic built-in self-tests (LBISTs) in which an LBIST controller provides control signals to multiple LBIST satellites that are co-located with different functional blocks of the device under test, such as processor cores in a multiprocessor integrated circuit. Because the data paths for each satellite are shorter than data paths in conventional LBIST architectures, fewer latches are needed to synchronize the delivery of data to scan chains in the satellites. In one embodiment, each satellite includes a pseudorandom bit pattern generator (PRPG,) scan chains and a multiple-input signature register (MISR). In one embodiment, the LBIST circuitry also includes a control scan chain that is coupled to each of the LBIST satellites and configured to scan data into and out of the LBIST satellites.

摘要翻译： 用于执行逻辑内置自检（LBIST）的系统和方法，其中LBIST控制器向与被测器件的不同功能块共同定位的多个LBIST卫星提供控制信号，例如多处理器集成中的处理器核 电路。 由于每个卫星的数据路径比常规LBIST架构中的数据路径短，因此需要较少的锁存器来同步数据传输到卫星中的扫描链。 在一个实施例中，每个卫星包括伪随机位模式生成器（PRPG），扫描链和多输入签名寄存器（MISR）。 在一个实施例中，LBIST电路还包括控制扫描链，其耦合到每个LBIST卫星并被配置为扫描数据进入和离开LBIST卫星。

公开(公告)号：US20070092048A1

公开(公告)日：2007-04-26

申请号：US11255155

申请日：2005-10-20

申请人： Nathan Chelstrom ,  Mack Riley ,  Shoji Sawamura

发明人： Nathan Chelstrom ,  Mack Riley ,  Shoji Sawamura

IPC分类号： H04L25/38

CPC分类号： H04L25/38

摘要： The present invention provides a data processing system, a method, and a computer program product for stopping at least two clock signals that oscillate at different frequencies and restarting the at least two clock signals at their correct phase. A RUNN counter stops the at least two clock signals. The RUNN counter stops the faster clock signal and restarts the faster clock signal at the correct phase. A phase status circuit determines the phase where the slower clock signal stopped and produces a phase status signal. A second circuit utilizes the phase status signal to start the slower clock signal at the correct phase. Therefore, the present invention insures that the faster clock signal and the slower clock signal are restarted at the correct phase. In another embodiment, the second circuit enables the present invention to start the slower clock signal at a desired phase.

摘要翻译： 本发明提供一种数据处理系统，方法和计算机程序产品，用于停止以不同频率振荡的至少两个时钟信号，并在其正确相位重新启动至少两个时钟信号。 RUNN计数器停止至少两个时钟信号。 RUNN计数器停止更快的时钟信号，并以正确的相位重新启动更快的时钟信号。 相位状态电路确定较慢时钟信号停止的相位，并产生相位状态信号。 第二个电路利用相位状态信号以正确的相位启动较慢的时钟信号。 因此，本发明确保更快的时钟信号和较慢的时钟信号在正确的相位重新启动。 在另一个实施例中，第二电路使本发明能够以期望的相位启动较慢的时钟信号。

公开(公告)号：US20060053348A1

公开(公告)日：2006-03-09

申请号：US10937689

申请日：2004-09-09

申请人： Nathan Chelstrom ,  Mack Riley ,  Michael Wang ,  Stephen Weitzel

发明人： Nathan Chelstrom ,  Mack Riley ,  Michael Wang ,  Stephen Weitzel

IPC分类号： G06F11/00

CPC分类号： G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  Y02D10/126

摘要： The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

公开(公告)号：US20070174679A1

公开(公告)日：2007-07-26

申请号：US11340448

申请日：2006-01-26

申请人： Nathan Chelstrom ,  Tilman Gloekler ,  Ralph Koester ,  Mack Riley

发明人： Nathan Chelstrom ,  Tilman Gloekler ,  Ralph Koester ,  Mack Riley

IPC分类号： G06F11/00

CPC分类号： G06F11/2236

摘要： A method and apparatus are disclosed for injecting errors in the functional units of a processor system, and for observing non-injected errors that occur in those functional units. A local error handler layer provides error injection for the various functional units at a local level. A global fault isolation register (FIR) layer couples to the local error handler layer to coordinate the handling of local errors in the multiple functional units of the processor system. A software debugger application or system software communicates with the global FIR layer to control error handling.

摘要翻译： 公开了一种用于在处理器系统的功能单元中注入错误并且用于观察在这些功能单元中发生的非注入错误的方法和装置。 本地错误处理程序层为本地级别的各种功能单元提供错误注入。 全局故障隔离寄存器（FIR）层耦合到本地错误处理器层，以协调对处理器系统的多个功能单元中的本地错误的处理。 软件调试器应用程序或系统软件与全局FIR层进行通信，以控制错误处理。

公开(公告)号：US20070091933A1

公开(公告)日：2007-04-26

申请号：US11255156

申请日：2005-10-20

申请人： Nathan Chelstrom ,  Mack Riley

发明人： Nathan Chelstrom ,  Mack Riley

IPC分类号： H04J3/06

CPC分类号： G06F1/12 ,  H04J3/0638 ,  H04L7/005 ,  H04L7/02

摘要： An apparatus and method for controlling asynchronous clock domains to perform synchronous operations are provided. With the system and method, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation, a manufacturing test sequence, debug operation, or the like.

摘要翻译： 提供了一种用于控制异步时钟域以执行同步操作的装置和方法。 利用该系统和方法，当在芯片上执行同步操作时，芯片的功能元件的锁存器由同步时钟控制，使得锁存器甚至跨越芯片的异步边界被同步地控制。 然后可以执行同步操作，并且在同步操作完成之后，芯片的功能元件以异步方式返回到由本地时钟控制。 该同步操作可以是例如上电复位（POR）操作，制造测试序列，调试操作等。

公开(公告)号：US20070146037A1

公开(公告)日：2007-06-28

申请号：US11318228

申请日：2005-12-22

申请人： Chiaki Takano ,  Daniel Stasiak ,  Nathan Chelstrom ,  Steven Ferguson

发明人： Chiaki Takano ,  Daniel Stasiak ,  Nathan Chelstrom ,  Steven Ferguson

IPC分类号： G06F1/04

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  Y02D10/126 ,  Y02D10/128

摘要： Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.

摘要翻译： 方法和装置提供：产生指示睡眠模式的第一基本上稳定的状态逻辑电平的控制信号，以及指示正常模式的第二基本稳定的逻辑电平; 当控制信号处于第一逻辑电平时产生处于基本稳态零电平的门信号，并且当控制信号处于第二逻辑电平时以当地时钟频率振荡; 根据门信号从系统时钟信号产生本地时钟信号; 并且在控制信号的原点与产生栅极信号的位置之间插入至少一个信号传播锁存电路。