摘要:
The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.
摘要:
An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.
摘要:
An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.
摘要:
Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed to determine whether any of the processor cores is malfunctioning. If none of the processor cores malfunctions, the processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor is fully functional. If one or more processor cores malfunctions, these processor cores are isolated and the remaining processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor operates properly with reduced functionality.
摘要:
A clock control hierarchy is provided that is comprised of synchronous and asynchronous hold request signals that are used to start and stop functional units of a chip. Pervasive logic is provided that uses a synchronous “chip hold” signal and asynchronous latch/functional unit hold signals to individually target functional units and latches that are to remain in a held state once the “chip hold” state is released. With the present invention, a chip hold request is first activated followed by scannable latch and non-scannable latch hold requests being activated to identify which latches will be clocked or not clocked when the chip hold is released. Functional unit hold signals are activated to place certain ones of the functional units of the chip in a hold state. The chip hold request is deactivated and the chip operates with the selected functional units and latches being maintained in a held state.
摘要:
An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.
摘要:
A method and apparatus are disclosed for injecting errors in the functional units of a processor system, and for observing non-injected errors that occur in those functional units. A local error handler layer provides error injection for the various functional units at a local level. A global fault isolation register (FIR) layer couples to the local error handler layer to coordinate the handling of local errors in the multiple functional units of the processor system. A software debugger application or system software communicates with the global FIR layer to control error handling.
摘要:
An apparatus and method for controlling asynchronous clock domains to perform synchronous operations are provided. With the system and method, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation, a manufacturing test sequence, debug operation, or the like.
摘要:
A system and method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device. With the system and method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.
摘要:
Systems and methods for performing logic built-in self-tests (LBISTs) in which an LBIST controller provides control signals to multiple LBIST satellites that are co-located with different functional blocks of the device under test, such as processor cores in a multiprocessor integrated circuit. Because the data paths for each satellite are shorter than data paths in conventional LBIST architectures, fewer latches are needed to synchronize the delivery of data to scan chains in the satellites. In one embodiment, each satellite includes a pseudorandom bit pattern generator (PRPG,) scan chains and a multiple-input signature register (MISR). In one embodiment, the LBIST circuitry also includes a control scan chain that is coupled to each of the LBIST satellites and configured to scan data into and out of the LBIST satellites.