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公开(公告)号：US20180267848A1
公开(公告)日：2018-09-20
申请号：US15981093
申请日：2018-05-16
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor： Rafael Castro Scorsi , Hector M. Rubio , Gerardo Daniel Domene-Ramirez
IPC: G06F11/07 , G06F11/00 , G05B19/418 , G06F13/24
CPC classification number: G06F11/0745 , G05B19/4183 , G05B2219/31282 , G05B2219/31284 , G06F11/006 , G06F11/0772 , G06F13/24 , Y02P90/10 , Y02P90/12
Abstract: A system may include a data acquisition hardware device (DAQ) for acquiring sample data and/or generating control signals, and a host system with memory that may store data samples and information associated with the DAQ and host system operations. The DAQ may push hardware status information to host memory, triggered by predetermined events taking place in the DAQ, e.g. timing events or interrupts. The DAQ may update dedicated buffers in host memory with status data for any of these events. The pushed status information may be read in a manner that allows detection of race conditions, and may be used to handle data acquisition, output control signaling, and interrupts as required without the host system having to query the DAQ. The DAQ may also detect data timing errors and report those data timing errors back to the host system, and also provide improved output operations using counters.
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公开(公告)号：US09996407B2
公开(公告)日：2018-06-12
申请号：US15087922
申请日：2016-03-31
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor： Rafael Castro Scorsi , Hector M. Rubio , Gerardo Daniel Domene-Ramirez
IPC: G06F13/28 , G06F11/07 , G05B19/418 , G06F13/24 , G06F11/00
CPC classification number: G06F11/0745 , G05B19/4183 , G05B2219/31282 , G05B2219/31284 , G06F11/006 , G06F11/0772 , G06F13/24 , Y02P90/10 , Y02P90/12
Abstract: A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory configured to store data samples and various data associated with the DAQ and processor operations. The DAQ device may push HW status information to host memory upon being triggered by predetermined events taking place in the DAQ device, e.g. timing events or interrupts, to avoid or reduce SW reads to the DAQ device. The DAQ device may update dedicated buffers in host memory with status data on any of these events. The status information pushed to memory may be read in a manner that allows detection of race conditions. Interrupts generated by the DAQ device may be similarly handled. Upon generating an interrupt, the DAQ device may gather information required to handle the interrupt, and push the information into system memory, along with information identifying the interrupt. SW may read system memory for this information, and handle the interrupts as required without having to query the DAQ device.
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公开(公告)号：US20160217028A1
公开(公告)日：2016-07-28
申请号：US15087922
申请日：2016-03-31
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor： Rafael Castro Scorsi , Hector M. Rubio , Gerardo Daniel Domene-Ramirez
CPC classification number: G06F11/0745 , G05B19/4183 , G05B2219/31282 , G05B2219/31284 , G06F11/006 , G06F11/0772 , G06F13/24 , Y02P90/10 , Y02P90/12
Abstract: A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory configured to store data samples and various data associated with the DAQ and processor operations. The DAQ device may push HW status information to host memory upon being triggered by predetermined events taking place in the DAQ device, e.g. timing events or interrupts, to avoid or reduce SW reads to the DAQ device. The DAQ device may update dedicated buffers in host memory with status data on any of these events. The status information pushed to memory may be read in a manner that allows detection of race conditions. Interrupts generated by the DAQ device may be similarly handled. Upon generating an interrupt, the DAQ device may gather information required to handle the interrupt, and push the information into system memory, along with information identifying the interrupt. SW may read system memory for this information, and handle the interrupts as required without having to query the DAQ device.
Abstract translation: 系统可以包括执行程序指令（SW）的处理单元，用于获取采样数据和/或产生控制信号的数据采集（DAQ）硬件设备，以及配置成存储与DAQ和处理器相关联的数据样本和各种数据的主机存储器 操作。 DAQ设备可以在由DAQ设备中发生的预定事件触发时将HW状态信息推送到主机存储器，例如。 定时事件或中断，以避免或减少对DAQ设备的SW读取。 DAQ设备可以更新主机存储器中的专用缓冲区，其中包含任何这些事件的状态数据。 推送到存储器的状态信息可以以允许检测竞态条件的方式被读取。 可以类似地处理由DAQ设备生成的中断。 在产生中断时，DAQ设备可以收集处理中断所需的信息，并将信息与识别中断的信息一起推送到系统存储器中。 SW可以读取该信息的系统内存，并根据需要处理中断，而无需查询DAQ设备。
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公开(公告)号：US12066971B2
公开(公告)日：2024-08-20
申请号：US17669708
申请日：2022-02-11
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor： Sundeep Chandhoke , Glen O. Sescila, III , Rafael Castro Scorsi
CPC classification number: G06F13/4282 , G06F9/4881 , G06F9/542 , G06F13/1673
Abstract: A network interface peripheral device (NIP) may include a network interface for communicating with a network, and an interconnect interface for communicating with a processor subsystem. First buffers in the NIP may hold data received from and/or distributed to peer peripherals by the NIP, and second buffers may hold payload data of scheduled data streams transmitted to and/or received from the network by the NIP. Payload data from the data in the first buffers may be stored in the second buffers and transmitted to the network according to transmit events generated based on a received schedule. Data may be received from the network according to receive events generated based on the received schedule, and distributed from the second buffers to the first buffers. A centralized system configuration entity may generate the schedule, manage configuration of the NIP, and coordinate the internal configuration of the NIP with a network configuration flow.
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公开(公告)号：US20150039272A1
公开(公告)日：2015-02-05
申请号：US13955523
申请日：2013-07-31
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor： Rafael Castro Scorsi , Kunal H. Patel , Hector Rubio
Abstract: A digitizer system (DS) may include one or more input channels to receive sample data, and an acquisition state machine (ASM) to organize the sample data into one or more acquisition records according to events of interest, and generate framing information corresponding to the one or more acquisition records. The events of interest may be identified by a trigger circuit in the DS, and relayed to the ASM for organizing the sample data. The DS may further include a data interface capable of receiving the one or more acquisition records and the framing information, encoding the one or more acquisition records and the framing information into encoded data, and transmitting the encoded data to an expansion module. The expansion module may receive the encoded data, decode the encoded data, and recover the sample data from the decoded data according to the framing information and the one or more acquisition records.
Abstract translation: 数字转换器系统（DS）可以包括用于接收采样数据的一个或多个输入通道，以及采集状态机（ASM），以根据感兴趣的事件将采样数据组织成一个或多个采集记录，并且生成对应于 一个或多个收购记录。 感兴趣的事件可以由DS中的触发电路来识别，并且被中继到ASM以组织样本数据。 DS还可以包括能够接收一个或多个捕获记录和成帧信息的数据接口，将一个或多个采集记录和成帧信息编码成编码数据，并将编码数据发送到扩展模块。 扩展模块可以接收编码数据，解码编码数据，并根据成帧信息和一个或多个采集记录从解码数据中恢复采样数据。
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Patent Agency Ranking
公开(公告)号：US08862795B2
公开(公告)日：2014-10-14
申请号：US14026007
申请日：2013-09-13
Applicant: National Instruments Corporation
Inventor： Rafael Castro Scorsi
CPC classification number: G06F5/065 , G06F5/16 , G06F13/1647 , G06F13/28
Abstract: System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes first and second memory banks. A first waveform is stored in chunks alternating between successive buffers in the first and second memory banks, and concurrently, the first and second chunks may be transferred to first and second FIFOs, respectively, which may be accumulated with respective first and second chunks of a second waveform into the first and second memory banks. This process may be repeated for respective successive pairs of the first and second waveforms, where the first and second memory banks and FIFOs are used in an alternating manner, and further, to accumulate additional waveforms, where previously stored (and accumulated) waveform data are accumulated chunkwise with successive additional waveform data, and where at least some of the accumulation is performed concurrently with waveform data transfers to and from the memory banks and FIFOs.
Abstract translation: 用于硬件实现的波形数据累积的系统和方法。 提供了包括第一和第二存储体的数字转换器。 第一波形以第一和第二存储体中的连续缓冲器之间交替存储的块中存储，并且同时，第一和第二块可以分别传送到第一和第二FIFO，其可以用相应的第一和第二块 第二波形进入第一和第二存储体。 可以针对第一和第二波形的相应连续对重复该过程，其中以交替方式使用第一和第二存储体和FIFO，并且还累积额外的波形，其中预先存储（和累积）波形数据是 与连续的附加波形数据块块累积，并且其中至少一些累积与到存储器组和FIFO的波形数据传输同时执行。
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公开(公告)号：US20220164306A1
公开(公告)日：2022-05-26
申请号：US17669708
申请日：2022-02-11
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor： Sundeep Chandhoke , Glen O. Sescila, III , Rafael Castro Scorsi
Abstract: A network interface peripheral device (NIP) may include a network interface for communicating with a network, and an interconnect interface for communicating with a processor subsystem. First buffers in the NIP may hold data received from and/or distributed to peer peripherals by the NIP, and second buffers may hold payload data of scheduled data streams transmitted to and/or received from the network by the NIP. Payload data from the data in the first buffers may be stored in the second buffers and transmitted to the network according to transmit events generated based on a received schedule. Data may be received from the network according to receive events generated based on the received schedule, and distributed from the second buffers to the first buffers. A centralized system configuration entity may generate the schedule, manage configuration of the NIP, and coordinate the internal configuration of the NIP with a network configuration flow.
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8.发明申请公开(公告)号：US20180276175A1
公开(公告)日：2018-09-27
申请号：US15466150
申请日：2017-03-22
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor： Sundeep Chandhoke , Glen O. Sescila, III , Rafael Castro Scorsi
CPC classification number: G06F13/4282 , G06F9/4881 , G06F9/542 , G06F13/1673
Abstract: A network interface peripheral device (NIP) may include a network interface for communicating with a network, and an interconnect interface for communicating with a processor subsystem. Peripheral data buffers (PDBs) in the NIP may hold data received from and/or distributed to peer peripherals by the NIP, and network data buffers (NDBs) may hold payload data of scheduled data streams transmitted to and/or received from the network by the NIP. A data handler in the NIP may generate the payload data from the data in the PDBs, and store the payload data in the NDBs according to scheduled data handler transmit events. The data handler may obtain the data from the payload data in the NDBs and store the obtained data in the PDBs according to scheduled data handler receive events. The NIP may include a mirrored finite state machine operating at the device level (of a device that may include the NIP) and controlled by a centralized system configuration entity to manage configuration of the NIP and coordinate the internal configuration of the NIP with a network configuration flow.
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公开(公告)号：US09323699B2
公开(公告)日：2016-04-26
申请号：US14149389
申请日：2014-01-07
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor： Rafael Castro Scorsi , Hector M. Rubio , Gerardo Daniel Domene-Ramirez
IPC: G06F13/28 , G06F13/24 , G05B19/418
CPC classification number: G06F11/0745 , G05B19/4183 , G05B2219/31282 , G05B2219/31284 , G06F11/006 , G06F11/0772 , G06F13/24 , Y02P90/10 , Y02P90/12
Abstract: A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory configured to store data samples and various data associated with the DAQ and processor operations. The DAQ device may push HW status information to host memory upon being triggered by predetermined events taking place in the DAQ device, e.g. timing events or interrupts, to avoid or reduce SW reads to the DAQ device. The DAQ device may update dedicated buffers in host memory with status data on any of these events. The status information pushed to memory may be read in a manner that allows detection of race conditions. Interrupts generated by the DAQ device may be similarly handled. Upon generating an interrupt, the DAQ device may gather information required to handle the interrupt, and push the information into system memory, along with information identifying the interrupt. SW may read system memory for this information, and handle the interrupts as required without having to query the DAQ device.
Abstract translation: 系统可以包括执行程序指令（SW）的处理单元，用于获取采样数据和/或产生控制信号的数据采集（DAQ）硬件设备，以及配置成存储与DAQ和处理器相关联的数据样本和各种数据的主机存储器 操作。 DAQ设备可以在由DAQ设备中发生的预定事件触发时将HW状态信息推送到主机存储器，例如。 定时事件或中断，以避免或减少对DAQ设备的SW读取。 DAQ设备可以更新主机存储器中的专用缓冲区，其中包含任何这些事件的状态数据。 推送到存储器的状态信息可以以允许检测竞态条件的方式被读取。 可以类似地处理由DAQ设备生成的中断。 在产生中断时，DAQ设备可以收集处理中断所需的信息，并将信息与识别中断的信息一起推送到系统存储器中。 SW可以读取该信息的系统内存，并根据需要处理中断，而无需查询DAQ设备。
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公开(公告)号：US08942300B1
公开(公告)日：2015-01-27
申请号：US13955523
申请日：2013-07-31
Applicant: National Instruments Corporation
Inventor： Rafael Castro Scorsi , Kunal H. Patel , Hector Rubio
Abstract: A digitizer system (DS) may include one or more input channels to receive sample data, and an acquisition state machine (ASM) to organize the sample data into one or more acquisition records according to events of interest, and generate framing information corresponding to the one or more acquisition records. The events of interest may be identified by a trigger circuit in the DS, and relayed to the ASM for organizing the sample data. The DS may further include a data interface capable of receiving the one or more acquisition records and the framing information, encoding the one or more acquisition records and the framing information into encoded data, and transmitting the encoded data to an expansion module. The expansion module may receive the encoded data, decode the encoded data, and recover the sample data from the decoded data according to the framing information and the one or more acquisition records.
Abstract translation: 数字转换器系统（DS）可以包括用于接收采样数据的一个或多个输入通道，以及采集状态机（ASM），以根据感兴趣的事件将采样数据组织成一个或多个采集记录，并且生成对应于 一个或多个收购记录。 感兴趣的事件可以由DS中的触发电路来识别，并且被中继到ASM以组织样本数据。 DS还可以包括能够接收一个或多个捕获记录和成帧信息的数据接口，将一个或多个采集记录和成帧信息编码成编码数据，并将编码数据发送到扩展模块。 扩展模块可以接收编码数据，解码编码数据，并根据成帧信息和一个或多个采集记录从解码数据中恢复采样数据。
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