利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.013 秒)

    JTAG instruction register and decoder for PLDS
    3.
    发明授权
    JTAG instruction register and decoder for PLDS 有权
    用于PLDS的JTAG指令寄存器和解码器

    公开(公告)号：US06804802B1

    公开(公告)日：2004-10-12

    申请号：US09599586

    申请日：2000-06-22

    申请人： Navaz Lulla ,  Anup Nayak

    发明人： Navaz Lulla ,  Anup Nayak

    IPC分类号： G01R3128

    CPC分类号： G01R31/318516 ,  G01R31/318555

    摘要： An apparatus comprising a synchronous circuit configured to (i) shift a JTAG instruction signal in response to a first control signal, (ii) decode the JTAG instruction signal while the JTAG instruction signal is shifted and (iii) latch the decoded JTAG instruction signal in response to a second control signal.

    摘要翻译： 一种装置，包括同步电路，其被配置为（i）响应于第一控制信号移位JTAG指令信号，（ii）在JTAG指令信号被移位的同时对JTAG指令信号进行解码，以及（iii）将解码的JTAG指令信号锁存在 对第二控制信号的响应。

    PLD configuration architecture
    5.
    发明授权
    PLD configuration architecture 有权
    PLD配置架构

    公开(公告)号：US06567970B1

    公开(公告)日：2003-05-20

    申请号：US09751234

    申请日：2000-12-27

    申请人： Anup Nayak ,  Navaz Lulla ,  Ramin Ighani ,  Rajiv Nema

    发明人： Anup Nayak ,  Navaz Lulla ,  Ramin Ighani ,  Rajiv Nema

    IPC分类号： G06F1750

    CPC分类号： G06F17/5054

    摘要： An apparatus comprising one or more configuration blocks. The configuration blocks (i) may comprise a number of configuration elements and (ii) may be configured to initiate reading or writing of the configuration elements in response to a control input.

    摘要翻译： 一种包括一个或多个配置块的设备。 配置块（i）可以包括多个配置元素，并且（ii）可以被配置为响应于控制输入而启动对配置元素的读取或写入。

    Configurable power controller
    6.
    发明授权
    Configurable power controller 有权
    可配置电源控制器

    公开(公告)号：US07863971B1

    公开(公告)日：2011-01-04

    申请号：US11998009

    申请日：2007-11-27

    申请人： Anup Nayak ,  Sanjay Kumar Sancheti ,  Shailja Garg

    发明人： Anup Nayak ,  Sanjay Kumar Sancheti ,  Shailja Garg

    IPC分类号： H03K17/74 ,  G11C5/14

    CPC分类号： H03K19/0016 ,  G06F1/3203 ,  G06F1/3287 ,  G11C5/14 ,  H03K17/74 ,  Y02D10/171

    摘要： A configurable power controller and method for controlling power of a macro circuit block, such as a memory circuit, in multiple power modes is described to help minimize power consumption of the macro circuit block when the application environment for the macro circuit block is in a lower power mode than during its normal power mode.

    摘要翻译： 描述了用于以多种功率模式来控制诸如存储器电路的宏电路块的功率的可配置功率控制器和方法，以在宏电路块的应用环境处于较低的状态时帮助最小化宏电路块的功率消耗 电源模式比正常电源模式。

    Method and system for generating a bit order data structure of configuration bits from a schematic hierarchy
    7.
    发明授权
    Method and system for generating a bit order data structure of configuration bits from a schematic hierarchy 有权
    用于从原理层级生成配置位的位顺序数据结构的方法和系统

    公开(公告)号：US06904436B1

    公开(公告)日：2005-06-07

    申请号：US09684160

    申请日：2000-10-04

    申请人： James Daniel Merchant ,  Gordon Carskadon ,  Brian P. Evans ,  Jeffery Scott Hunt ,  Anup Nayak ,  Andrew Wright

    发明人： James Daniel Merchant ,  Gordon Carskadon ,  Brian P. Evans ,  Jeffery Scott Hunt ,  Anup Nayak ,  Andrew Wright

    IPC分类号： G06F7/08 ,  G06F17/50

    CPC分类号： G06F17/5054 ,  Y10S707/956 ,  Y10S707/99942

    摘要： A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device. Next, this embodiment orders the plurality of logical names based on the order specified in the database from the previous step.

    摘要翻译： 一种用于自动构建可编程逻辑器件的配置位的位顺序数据结构的方法和系统。 本发明的一个实施例首先以可编程设备的分层示意图表示识别多个存储器单元。 接下来，本实施例确定与多个存储单元对应的多个地址。 该实施例接下来确定多个存储单元的多个逻辑名称。 然后，基于将多个地址加载到可编程逻辑器件中的顺序，本实施例对多个存储器单元定义多个逻辑名称。 另一个实施例首先访问包括与多个地址对应的多个逻辑名称的数据库。 然后，本实施例访问指定将多个地址加载到可编程逻辑器件中的顺序的数据库。 接下来，本实施例基于从前一步骤在数据库中指定的顺序来订购多个逻辑名称。

    Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals
    8.
    发明授权
    Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals 有权
    基于这种时钟信号的频率差选择多个时钟信号之一的方法和装置

    公开(公告)号：US07343510B1

    公开(公告)日：2008-03-11

    申请号：US11019731

    申请日：2004-12-21

    申请人： Mark Ross ,  S. Babar Raza ,  Dimitris Pantelakis ,  Anup Nayak ,  Walter Bridgewater

    发明人： Mark Ross ,  S. Babar Raza ,  Dimitris Pantelakis ,  Anup Nayak ,  Walter Bridgewater

    IPC分类号： G06F1/12

    CPC分类号： G06F1/04

    摘要： A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second count value CNT2 according to a second clock signal CLK2. First separation-detect logic (102-0) and second separation-detect logic (102-1) determine if a pre-specified difference exists between a first count value (CNT1/CNT1′) and second count value (CNT2/CNT2′). According to such determinations, separation information (INF—1 and INF—2) can be generated indicating which clock signal (CLK1 or CLK2) is faster. Selection logic (106) can select a faster of the clock signals (CLK1 or CLK2) if the separation information values confirm one another.

    摘要翻译： 时钟检测和选择电路（100）可以包括根据第一时钟信号CLK 1产生第一计数值CNT 1的第一计数器（102-0）和产生第二计数值的第二计数器（102-1） CNT 2根据第二时钟信号CLK 2。 第一分离检测逻辑（102-0）和第二分离检测逻辑（102-1）确定在第一计数值（CNT 1 / CNT 1'）和第二计数值（CNT 2 / CNT 2'）。 根据这样的确定，可以产生指示哪个时钟信号（CLK 1或CLK 2）更快的分离信息（INF＆gt; 1＆lt; 1＆gt; 1和INF＆gt; 2）。 如果分离信息值彼此确认，则选择逻辑（106）可选择更快的时钟信号（CLK 1或CLK 2）。

    Programmable interconnect matrix architecture for complex programmable logic device
    9.
    发明授权
    Programmable interconnect matrix architecture for complex programmable logic device 失效
    用于复杂可编程逻辑器件的可编程互连矩阵架构

    公开(公告)号：US06370140B1

    公开(公告)日：2002-04-09

    申请号：US09009137

    申请日：1998-01-20

    申请人： Anup Nayak

    发明人： Anup Nayak

    IPC分类号： H03K19173

    CPC分类号： H03K19/17736

    摘要： A routing architecture which includes a plurality of switching elements grouped so as to provide one or more outputs for a plurality of inputs, wherein the grouping represents a hierarchy of selection levels. The routing architecture may be configured such that at each of the selection levels fewer outputs are provided than inputs are received. The selection levels may be implemented using one or more multiplexers at each of the levels. The routing architecture may be embodied in a programmable logic device which may also include a number of logic blocks. Each of the logic blocks may be coupled to receive at least one of the outputs of the routing architecture and the programmable logic device may be configured so that a subset of the plurality of inputs to the routing architecture are provided by one or more of the logic blocks.

    摘要翻译： 一种路由架构，其包括被分组以便为多个输入提供一个或多个输出的多个开关元件，其中所述分组表示选择级别的层级。 路由架构可以被配置为使得在每个选择级别提供比输入被接收的更少的输出。 可以使用在每个级别的一个或多个多路复用器来实现选择级别。 路由架构可以体现在可以包括多个逻辑块的可编程逻辑设备中。 每个逻辑块可以被耦合以接收路由架构的输出中的至少一个，并且可编程逻辑设备可以被配置为使得路由架构的多个输入的子集由逻辑中的一个或多个提供 块。

    Configuration bit read/write data shift register
    10.
    发明授权
    Configuration bit read/write data shift register 有权
    配置位读/写数据移位寄存器

    公开(公告)号：US06351139B1

    公开(公告)日：2002-02-26

    申请号：US09541322

    申请日：2000-04-01

    申请人： Ramin Ighani ,  Anup Nayak

    发明人： Ramin Ighani ,  Anup Nayak

    IPC分类号： G06F738

    CPC分类号： G11C7/1006 ,  G11C7/1036

    摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) generate one or more first parallel data signals in response to a first serial data stream and a first control signal and (ii) generate a second serial data stream in response to one or more second parallel data signals and a second control signal. The second circuit may be configured to write the one or more first parallel data signals to and read the one or more second parallel data signals from an array of storage elements in response to one or more control signals.

    摘要翻译： 一种包括第一电路和第二电路的装置。 第一电路可以被配置为（i）响应于第一串行数据流和第一控制信号而产生一个或多个第一并行数据信号，并且（ii）响应于一个或多个第二并行数据产生第二串行数据流 信号和第二控制信号。 第二电路可以被配置为响应于一个或多个控制信号将一个或多个第一并行数据信号写入存储元件阵列并从其中读出一个或多个第二并行数据信号。