公开(公告)号：US20060039217A1

公开(公告)日：2006-02-23

申请号：US10921754

申请日：2004-08-17

申请人： Neal Berger ,  George Chang ,  Pearl Cheng ,  Anne Koh

发明人： Neal Berger ,  George Chang ,  Pearl Cheng ,  Anne Koh

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/1027 ,  G11C7/103

摘要： An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit. The control circuit receives a read command, and a clock signal, and in response to the read command activates a first plurality (j) of the plurality (k) of sense amplifiers (j

摘要翻译： 集成电路存储器件具有以多个阵列排列的多个存储单元。 每个阵列具有多个行，多个列线以及连接到每个阵列中的存储器单元的多条行线。 阵列中的存储单元可由列线和行行寻址。 列地址解码器接收列地址信号并且响应地选择每个阵列的一个或多个列线。 行地址解码器接收行地址信号并且响应地选择每个阵列的行线。 存储器件还具有多个（k）个读出放大器，其中一个读出放大器与每个阵列相关联，可连接到阵列的一个或多个列线，并接收从寻址的存储器单元提供的信号。 存储器件还具有寄存器; 和控制电路。 控制电路接收读取命令，并且时钟信号，并且响应于读取命令，激活多个（k）个读出放大器（k）中的第一个（j）一段足以感测信号的时间段 在与多个（j）个读出放大器中的每一个相关联的连接列线上。 控制电路将信号锁存到寄存器中; 并且去激活所述第一多个（j）读出放大器; 并响应于时钟信号串行输出来自寄存器的信号。

公开(公告)号：US20060039216A1

公开(公告)日：2006-02-23

申请号：US10893809

申请日：2004-07-19

申请人： Neal Berger ,  George Chang ,  Pearl Cheng ,  Anne Koh

发明人： Neal Berger ,  George Chang ,  Pearl Cheng ,  Anne Koh

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： An integrated circuit memory device has an array of memory cells arranged in a plurality of rows and columns and a plurality of row lines and a plurality of column lines. Cells arranged in the same row are connected by a common row line, and cells arranged in the same column are connected by a common column line. Each cell in the array is addressed by an address signal which has a plurality of bits. A sense amplifier circuit is connectable to one or more of the plurality of column lines of the array. An address input terminal receives in series the plurality of bits of the address signal. Each of the column lines is connectable to a pre-charge voltage, in response to a read command. A decoder circuit receives the address signal and decodes the address signal as each of the plurality of bits is received and disconnects certain of the column lines to the pre-charge voltage in response to the decoding, and activates the sense amplifier circuit after all of the plurality of bits of the address signal are received.

摘要翻译： 集成电路存储器件具有排列成多个行和列以及多条行线和多条列线的存储单元阵列。 布置在同一行中的单元通过公共行线连接，并且排列在同一列中的单元通过公共列线连接。 阵列中的每个单元由具有多个位的地址信号来寻址。 读出放大器电路可连接到阵列的多个列线中的一个或多个。 地址输入端串联地址信号的多个位。 响应读取命令，每列列线可连接到预充电电压。 解码器电路接收地址信号并且在接收到多个比特中的每一个时对地址信号进行解码，并且响应于解码将某些列线断开到预充电电压，并且在全部 接收地址信号的多个位。

公开(公告)号：US5530803A

公开(公告)日：1996-06-25

申请号：US227755

申请日：1994-04-14

申请人： George Chang ,  Pearl Cheng

发明人： George Chang ,  Pearl Cheng

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C16/02 ,  G11C16/10 ,  G06F11/00

CPC分类号： G11C16/10

摘要： A method for programming an integrated memory circuit and an integrated memory circuit structure for storing information are disclosed. The method of programming includes the steps of providing a program mode for programming the memory cells in accordance with total number of memory cells that is required to be programmed; and programming the memory cells in accordance with the program mode. The integrated memory circuit includes a program mode determining circuit, and a programming circuit operatively coupled to the program mode determining circuit for programming each of a plurality of block of memory cells according to its respective program mode. The program mode determining circuit comprises a circuit for determining the total number of memory cells that is required to be programmed in each block and a control circuit operatively coupled to the memory cells determining circuit for providing a first program mode control signal, a plurality of second program mode control signals and a third program mode control signal, if the total number of memory cells that are required to be programmed in a block is greater than zero but is less than or equal to a threshold number N, greater than the threshold number N, and equal to zero, respectively. Through the use of the programming method and the integrated memory circuit design, the requirement of additional number or increased current capacities of drain pumps associated with programming the integrated circuit is eliminated which reduces design complexity and minimizes the size of the integrated circuit.

摘要翻译： 公开了一种用于编程集成存储器电路的方法和用于存储信息的集成存储器电路结构。 编程方法包括以下步骤：根据需要编程的存储器单元的总数来提供用于对存储器单元进行编程的编程模式; 并根据程序模式编程存储单元。 集成存储器电路包括程序模式确定电路和可操作地耦合到程序模式确定电路的编程电路，用于根据其相应的程序模式对多个存储器单元块中的每一个进行编程。 程序模式确定电路包括用于确定需要在每个程序段中编程的存储器单元的总数的电路和可操作地耦合到存储单元确定电路的控制电路，用于提供第一编程模式控制信号，多个第二 程序模式控制信号和第三程序模式控制信号，如果要在块中编程的存储器单元的总数大于零但小于或等于阈值数N，则大于阈值数N ，并分别等于零。 通过使用编程方法和集成存储器电路设计，消除了与编程集成电路相关联的排水泵的附加数量或增加的电流容量的要求，这降低了设计复杂性并使集成电路的尺寸最小化。

公开(公告)号：US20090080275A1

公开(公告)日：2009-03-26

申请号：US11858515

申请日：2007-09-20

申请人： Chinh Vo ,  Harry Shengwen Luan ,  Pearl Cheng

发明人： Chinh Vo ,  Harry Shengwen Luan ,  Pearl Cheng

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C16/10

摘要： In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.

摘要翻译： 在示例实施例中，提供了用于减少位线泄漏电流的方法。 在示例实施例中，未选择的程序字线被偏置到偏置电压。 未选择的程序字线连接到存储单元，并且存储单元包括多个晶体管。 在另一个示例性实施例中，在读取操作期间将未选择的存储单元偏置到负偏置电压。

公开(公告)号：US07586787B2

公开(公告)日：2009-09-08

申请号：US11858515

申请日：2007-09-20

申请人： Chinh Vo ,  Harry Shengwen Luan ,  Pearl Cheng

发明人： Chinh Vo ,  Harry Shengwen Luan ,  Pearl Cheng

IPC分类号： G11C16/04

CPC分类号： G11C7/12 ,  G11C16/10

摘要： In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.

摘要翻译： 在示例实施例中，提供了用于减少位线泄漏电流的方法。 在示例实施例中，未选择的程序字线被偏置到偏置电压。 未选择的程序字线连接到存储单元，并且存储单元包括多个晶体管。 在另一个示例性实施例中，在读取操作期间将未选择的存储单元偏置到负偏置电压。

公开(公告)号：US4460982A

公开(公告)日：1984-07-17

申请号：US380149

申请日：1982-05-20

申请人： Lubin Gee ,  Pearl Cheng ,  Yogendra Bobra ,  Rustam Mehta

发明人： Lubin Gee ,  Pearl Cheng ,  Yogendra Bobra ,  Rustam Mehta

IPC分类号： G11C16/10 ,  G11C16/14 ,  G11C16/32 ,  G11C11/40

CPC分类号： G11C16/32 ,  G11C16/10 ,  G11C16/14

摘要： An E.sup.2 PROM is disclosed which provides automatic programming verification. Before data is written into the cells, the cells are automatically erased. The contents of the cells are checked to verify that erasing has been completed. If it has not, erasing is continued until the cells are erased. When data is written into the cells, the writing of the data into the cells continues until programming is verified. The verification is conducted at potentials other than the normal reference potential to assure that the cells are well programmed with either binary zeroes or binary ones.

摘要翻译： 公开了一种提供自动编程验证的E2PROM。 在将数据写入单元格之前，单元将被自动擦除。 检查单元的内容以验证擦除是否已完成。 如果没有，则继续擦除直到单元被擦除。 当数据写入单元格时，将数据写入单元继续，直到编程被验证。 验证在除了正常参考电位之外的电位下进行，以确保电池具有二进制零或二进制零编程。