公开(公告)号：US5287435A

公开(公告)日：1994-02-15

申请号：US572214

申请日：1990-08-23

申请人： Nissan Cohen ,  Gill Barequet ,  Daniel Barnea ,  Barry Ben-Ezra ,  Yehoshua Dollberg ,  Shalev Gilad ,  Varda Herskowits ,  Herbert Meininger ,  Itzik Pomerantz ,  Benjamin Sas ,  Yehoshua Sheinman ,  Mark Shlick ,  Michael Wasserstein ,  Nachshon Yeshurun

发明人： Nissan Cohen ,  Gill Barequet ,  Daniel Barnea ,  Barry Ben-Ezra ,  Yehoshua Dollberg ,  Shalev Gilad ,  Varda Herskowits ,  Herbert Meininger ,  Itzik Pomerantz ,  Benjamin Sas ,  Yehoshua Sheinman ,  Mark Shlick ,  Michael Wasserstein ,  Nachshon Yeshurun

IPC分类号： B29C67/00 ,  G06F15/00 ,  B28B17/00 ,  G06K9/00

CPC分类号： B29C67/007 ,  B29C67/0092 ,  G05B2219/49015

摘要： Apparatus for producing a three-dimensional model including apparatus for depositing, layer upon layer, a photopolymer material in a selectable configuration and apparatus for curing each photopolymer layer following deposition thereof and prior to deposition thereon of a succeeding layer of photopolymer.

摘要翻译： 一种用于生产三维模型的装置，包括用于以可选择的构造沉积，一层一层的光聚合物材料的设备，以及用于在其沉积之后以及在其上沉积下一层光聚合物之前固化每个光聚合物层的装置。

公开(公告)号：US20090172498A1

公开(公告)日：2009-07-02

申请号：US12005368

申请日：2007-12-27

申请人： Mark Shlick ,  Mark Murin ,  Menahem Lasser

发明人： Mark Shlick ,  Mark Murin ,  Menahem Lasser

IPC分类号： G11C29/00

CPC分类号： G06F11/1064

摘要： A method of storage and retrieval of data in a flash memory system, the flash memory system comprising a cache storage area of relatively high reliability, and a main storage area of relatively low reliability, the method comprising adding to data a level of error correction redundancy higher by a predetermined margin than that required for the cache storage area, writing the data to the cache storage area, and from the cache storage area copying the data directly to the main storage area, the predetermined margin being such as to allow subsequent error correction to compensate for errors accumulated from the cache storage area and the main storage area. In this way the memory die copy back operation can be used for copying the data from the cache to the main memory and two out of four transfers over the data bus to the flash controller are avoided.

摘要翻译： 一种在闪速存储器系统中存储和检索数据的方法，所述闪速存储器系统包括相对较高可靠性的高速缓存存储区域和相对较低可靠性的主存储区域，所述方法包括向数据添加纠错冗余级别 高于高速缓存存储区域所需的预定余量，将数据写入高速缓存存储区域，并从高速缓存存储区域将数据直接复制到主存储区域，预定余量允许后续纠错 以补偿从高速缓存存储区域和主存储区域累积的错误。 以这种方式，可以使用存储器管芯复制操作来将数据从高速缓存复制到主存储器，并且避免通过数据总线向闪存控制器传输四次。

公开(公告)号：US20080285351A1

公开(公告)日：2008-11-20

申请号：US11945167

申请日：2007-11-26

申请人： Mark Shlick ,  Menahem Lasser

发明人： Mark Shlick ,  Menahem Lasser

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C11/5621 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2211/5634

摘要： A threshold voltage distribution of a set of storage elements in a memory device is measured by sweeping a control gate voltage while measuring a characteristic of the set of storage elements as a whole. The characteristic indicates how many of the storage elements meet a given condition, such as being in a conductive state. For example, the characteristic may be a combined current, voltage or capacitance of the set which is measured at a common source of the set. The control gate voltage can be generated internally within a memory die. Similarly, the threshold voltage distribution can be determined internally within the memory die. Optionally, storage elements which become conductive can be locked out, such as by changing a bit line voltage, so they no longer contribute to the characteristic. New read reference voltages are determined based on the threshold voltage distribution to reduce errors in future read operations.

摘要翻译： 通过扫描控制栅极电压同时测量该组存储元件的整体的特性来测量存储器件中的一组存储元件的阈值电压分布。 该特性表示存储元件中有多少满足给定条件，例如处于导通状态。 例如，该特性可以是在集合的公共源处测量的组合的电流，电压或电容。 控制栅极电压可以在存储管芯内部产生。 类似地，可以在存储管芯内部确定阈值电压分布。 可选地，变得导电的存储元件可以被锁定，例如通过改变位线电压，因此它们不再有助于特性。 基于阈值电压分布确定新的读取参考电压，以减少将来读取操作中的错误。

公开(公告)号：US08112682B2

公开(公告)日：2012-02-07

申请号：US12428485

申请日：2009-04-23

申请人： Menahem Lasser ,  Mark Shlick

发明人： Menahem Lasser ,  Mark Shlick

IPC分类号： G11C29/00

CPC分类号： G11C29/26 ,  G11C16/04 ,  G11C29/08 ,  G11C2029/0409

摘要： Apparatus and methods for effecting bad-block testing operations are disclosed herein. In some embodiments, instead of effecting bad-block testing for the majority of the flash memory blocks of a flash memory device during manufacture, most or all bad-block testing is postponed until the end user is in possession of the flash memory device. In some embodiments, after user data is received by the flash memory device from a host device, one or more blocks of the flash memory device are subjected to bad-block testing.

摘要翻译： 本文公开了用于实施坏块测试操作的装置和方法。 在一些实施例中，代替在制造期间对闪存设备的大多数快闪存储器块进行坏块测试，绝大多数或全部坏块测试被推迟直到最终用户拥有闪存器件。 在一些实施例中，在闪存设备从主机设备接收到用户数据之后，对闪存设备的一个或多个块进行坏块测试。

公开(公告)号：US07865658B2

公开(公告)日：2011-01-04

申请号：US11967369

申请日：2007-12-31

申请人： Menahem Lasser ,  Itshak Afriat ,  Opher Lieber ,  Mark Shlick

发明人： Menahem Lasser ,  Itshak Afriat ,  Opher Lieber ,  Mark Shlick

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0893 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/1024 ,  G06F2212/313 ,  G06F2212/7203 ,  G06F2212/7208

摘要： A method and system for balancing host write operations and cache flushing is disclosed. The method may include steps of determining an available capacity in a cache storage portion of a self-caching storage device, determining a ratio of cache flushing steps to host write commands if the available capacity is below a desired threshold and interleaving cache flushing steps with host write commands to achieve the ratio. The cache flushing steps may be executed by maintaining a storage device busy status after executing a host write command and utilizing this additional time to copy a portion of the data from the cache storage into the main storage. The system may include a cache storage, a main storage and a controller configured to determine and execute a ratio of cache flushing steps to host write commands by executing cache flushing steps while maintaining a busy status after a host write command.

摘要翻译： 公开了一种用于平衡主机写入操作和缓存冲洗的方法和系统。 该方法可以包括以下步骤：确定自缓存存储设备的高速缓存存储部分中的可用容量，如果可用容量低于期望阈值，则确定高速缓存刷新步骤与主机写入命令的比率，并且与主机交织高速缓存刷新步骤 写命令来实现比例。 可以通过在执行主机写入命令之后维持存储设备忙状态并利用该附加时间将数据的一部分从高速缓存存储器复制到主存储器中来执行高速缓冲存储器刷新步骤。 该系统可以包括高速缓存存储器，主存储器和控制器，该控制器被配置为通过在主机写入命令之后保持忙状态的同时执行高速缓冲存储器刷新步骤来确定和执行高速缓存刷新步骤以主机写入命令的比率。

公开(公告)号：US07613045B2

公开(公告)日：2009-11-03

申请号：US11945120

申请日：2007-11-26

申请人： Mark Murin ,  Mark Shlick ,  Menahem Lasser ,  Cuong Trinh

发明人： Mark Murin ,  Mark Shlick ,  Menahem Lasser ,  Cuong Trinh

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5631 ,  G11C2211/5634

摘要： A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using a reference voltage which is different than a reference voltage used in a previous reading, where the new read reference value is not explicitly set outside the memory device. In one implementation, the memory device is provided with an initial reference voltage and a step size for generating additional reference voltages. The technique can be used, e.g., in determining a threshold voltage distribution of a set of storage elements. In this case, a voltage sweep can be applied to a word line associated with the set of storage elements, and data obtained based on the number of conductive storage elements.

摘要翻译： 存储器件产生一个或多个读取参考电压，而不是明确地提供来自外部主机控制器的每个读取参考电压。 该技术涉及向存储器件提供命令，其使得存储器件使用不同于先前读取中使用的参考电压的参考电压来读取一组存储元件，其中新的读取参考值不是明确的 设置在存储设备外面。 在一个实现中，存储器件被提供有初始参考电压和用于产生附加参考电压的步长。 该技术可以用于例如确定一组存储元件的阈值电压分布。 在这种情况下，可以对与该组存储元件相关联的字线施加电压扫描，并且可以基于导电存储元件的数量获得的数据。

公开(公告)号：US20080259684A1

公开(公告)日：2008-10-23

申请号：US11806111

申请日：2007-05-30

申请人： Mark Shlick ,  Mark Murin

发明人： Mark Shlick ,  Mark Murin

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621 ,  G11C2211/5648

摘要： When a memory device receives two or more pluralities of bits from a host to store in a nonvolatile memory, the device first stores the bits in a volatile memory. Then, in storing the bits in the nonvolatile memory, the device raises the threshold voltages of some cells of the volatile memory to values above a verify voltage. While those threshold voltages remain substantially at those levels, the device raises the threshold voltages of other cells of the volatile memory to values below the verify voltage. In the end, every cell stores one or more bits from each plurality of bits. Preferably, all the cells share a common wordline. A data storage device operates similarly with respect to storing pluralities of bits generated by an application running on the system.

摘要翻译： 当存储器装置从主机接收两个或多个多个比特以存储在非易失性存储器中时，该装置首先将该比特存储在易失性存储器中。 然后，在将位存储在非易失性存储器中时，该器件将易失性存储器的一些单元的阈值电压提高到高于验证电压的值。 当这些阈值电压基本保持在这些电平时，器件将易失性存储器的其他单元的阈值电压升高到低于验证电压的值。 最后，每个单元存储来自每个位的一个或多个位。 优选地，所有细胞共享公共字线。 数据存储设备的操作类似地存储由在系统上运行的应用程序生成的多个位。

公开(公告)号：US08125833B2

公开(公告)日：2012-02-28

申请号：US12964286

申请日：2010-12-09

申请人： Eran Sharon ,  Idan Alrod ,  Mark Shlick

发明人： Eran Sharon ,  Idan Alrod ,  Mark Shlick

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

摘要： A data storage device includes a controller and storage elements. The controller is configured to read a threshold voltage of each of a plurality of the storage elements to generate read threshold data and to assign reference voltages defining each of a plurality of voltage threshold states based on the read threshold data.

摘要翻译： 数据存储装置包括控制器和存储元件。 控制器被配置为读取多个存储元件中的每一个的阈值电压以产生读取阈值数据，并且基于读取的阈值数据分配定义多个电压阈值状态中的每一个的参考电压。

公开(公告)号：US08073648B2

公开(公告)日：2011-12-06

申请号：US11945167

申请日：2007-11-26

申请人： Mark Shlick ,  Menahem Lasser

发明人： Mark Shlick ,  Menahem Lasser

IPC分类号： G01R31/14

CPC分类号： G11C11/5621 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2211/5634

摘要： A threshold voltage distribution of a set of storage elements in a memory device is measured by sweeping a control gate voltage while measuring a characteristic of the set of storage elements as a whole. The characteristic indicates how many of the storage elements meet a given condition, such as being in a conductive state. For example, the characteristic may be a combined current, voltage or capacitance of the set which is measured at a common source of the set. The control gate voltage can be generated internally within a memory die. Similarly, the threshold voltage distribution can be determined internally within the memory die. Optionally, storage elements which become conductive can be locked out, such as by changing a bit line voltage, so they no longer contribute to the characteristic. New read reference voltages are determined based on the threshold voltage distribution to reduce errors in future read operations.

摘要翻译： 通过扫描控制栅极电压同时测量该组存储元件的整体的特性来测量存储器件中的一组存储元件的阈值电压分布。 该特性表示存储元件中有多少满足给定条件，例如处于导通状态。 例如，该特性可以是在集合的公共源处测量的组合的电流，电压或电容。 控制栅极电压可以在存储管芯内部产生。 类似地，可以在存储管芯内部确定阈值电压分布。 可选地，变得导电的存储元件可以被锁定，例如通过改变位线电压，因此它们不再有助于特性。 基于阈值电压分布确定新的读取参考电压，以减少将来读取操作中的错误。

公开(公告)号：US07876621B2

公开(公告)日：2011-01-25

申请号：US11941946

申请日：2007-11-18

申请人： Eran Sharon ,  Idan Alrod ,  Mark Shlick

发明人： Eran Sharon ,  Idan Alrod ,  Mark Shlick

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

摘要： Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. A histogram is constructed by determining how many of some or all of the cells have threshold voltages in each of two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on estimated values of shape parameters of the histogram. Alternatively, the cells are read relative to reference voltages that define m≧2 threshold voltage intervals that span the threshold voltage window, to determine numbers of at least a portion of the cells whose threshold voltages are in each of two or more of the threshold voltage intervals. Respective threshold voltage states are assigned to the cells based on the numbers without re-reading the cells.

摘要翻译： 多个闪存单元中的每一个被编程为阈值电压窗口内的L≥2个阈值电压状态中的相应一个。 通过确定在阈值电压窗口内的两个或多个m≥2个阈值电压间隔中的每一个中的一些或全部单元中有多少个具有阈值电压来构造直方图。 基于直方图的形状参数的估计值来选择用于读取单元的参考电压。 或者，相对于限定跨越阈值电压窗口的m≥2个阈值电压间隔的参考电压来读取单元，以确定其阈值电压在阈值电压中的两个或更多个中的每一个中的至少一部分单元的数量 间隔 基于数字将各个阈值电压状态分配给单元，而不重新读取单元。