公开(公告)号：US20090210586A1

公开(公告)日：2009-08-20

申请号：US12320954

申请日：2009-02-10

申请人： Noboru Tanabe

发明人： Noboru Tanabe

IPC分类号： G06F3/00

CPC分类号： H04L49/9063 ,  H04L45/745 ,  H04L49/90 ,  H04L49/9021 ,  H04L49/9073

摘要： A communication control device includes a plurality of receive buffers each storing therein received information that corresponds to all or a part of a received message or an argument of a receive function, a hash-value generating unit that generates a hash value from a receive key contained in the received message in accordance with a hash-value generation rule, a storing unit that stores the received information in a selected one of the receive buffers corresponding to the hash value, and an output unit that outputs the received information from one of the receive buffers corresponding to the hash value in response to a transmission request from a receiving unit that performs a receiving operation by determining a matching based on a receive key specified by the receive function.

摘要翻译： 通信控制装置包括多个接收缓冲器，每个接收缓冲器存储其中接收到的与接收到的消息的全部或一部分或接收功能的参数相对应的信息，散列值生成单元，其从包含的接收密钥生成散列值 在根据哈希值生成规则的接收到的消息中，存储单元，其将所接收的信息存储在与所述散列值相对应的所述接收缓冲器中的所选择的一个中;以及输出单元，其从所述接收 响应于来自执行接收操作的接收单元的发送请求，基于由接收功能指定的接收键确定匹配，对应于散列值的缓冲器。

公开(公告)号：US5488735A

公开(公告)日：1996-01-30

申请号：US906220

申请日：1992-06-26

申请人： Noboru Tanabe ,  Shigeru Oyanagi ,  Shinichi Baba ,  Katsuji Kaminishi ,  Masaru Nakamura ,  Kazunori Sekido

发明人： Noboru Tanabe ,  Shigeru Oyanagi ,  Shinichi Baba ,  Katsuji Kaminishi ,  Masaru Nakamura ,  Kazunori Sekido

IPC分类号： H01L31/12 ,  H01L33/00 ,  H01L33/06 ,  H01L33/08 ,  H01L33/10 ,  H01L33/20 ,  H01L33/30 ,  H01L33/58 ,  H01L33/60 ,  H04B10/112 ,  H04B10/27 ,  H04B10/275 ,  H04B10/278 ,  H04B10/54 ,  H04B10/556 ,  H04B10/572 ,  H04B10/80 ,  H04Q11/00 ,  G06F13/00

CPC分类号： H04Q11/0003 ,  H04Q2011/0007 ,  H04Q2011/0024 ,  H04Q2011/0026 ,  H04Q2011/0039 ,  H04Q2011/0052

摘要： An optical interconnection capable of realizing smooth data transmissions among micro-processors provided on a plurality of processor boards. An optical interconnection includes: a series of optical devices, provided on the processor boards separately, each optical device on each processor board being connected with the processor elements provided on that processor board and including a multiplicity of optical element cells for intercepting light signals from a first side of the optical device, transmitting intercepted light signals to a second side of the optical device, and emitting light signals to the second side of the optical device; and an optical path for optically connecting the optical devices such that light signals coming from the second side of one optical device are intercepted at the first side of another optical device.

摘要翻译： 一种能够实现在多个处理器板上提供的微处理器之间的平滑数据传输的光互连。 光互连包括：分开设置在处理器板上的一系列光学器件，每个处理器板上的每个光学器件与设置在该处理器板上的处理器元件连接，并且包括多个光学元件单元，用于截取来自 将遮断的光信号发送到光学装置的第二侧，并将光信号发射到光学装置的第二侧; 以及用于光学连接光学装置的光路，使得来自一个光学装置的第二侧的光信号在另一个光学装置的第一侧被截取。

公开(公告)号：US08423689B2

公开(公告)日：2013-04-16

申请号：US12320954

申请日：2009-02-10

申请人： Noboru Tanabe

发明人： Noboru Tanabe

IPC分类号： G06F3/00 ,  G06F7/00

CPC分类号： H04L49/9063 ,  H04L45/745 ,  H04L49/90 ,  H04L49/9021 ,  H04L49/9073

摘要： A communication control device includes a plurality of receive buffers each storing therein received information that corresponds to all or a part of a received message or an argument of a receive function, a hash-value generating unit that generates a hash value from a receive key contained in the received message in accordance with a hash-value generation rule, a storing unit that stores the received information in a selected one of the receive buffers corresponding to the hash value, and an output unit that outputs the received information from one of the receive buffers corresponding to the hash value in response to a transmission request from a receiving unit that performs a receiving operation by determining a matching based on a receive key specified by the receive function.

公开(公告)号：US06874033B1

公开(公告)日：2005-03-29

申请号：US09622484

申请日：1998-03-23

申请人： Kazuo Sugai ,  Takeshi Aimoto ,  Nobuhito Matsuyama ,  Shinichi Akahane ,  Noboru Tanabe ,  Yoshihito Sako

发明人： Kazuo Sugai ,  Takeshi Aimoto ,  Nobuhito Matsuyama ,  Shinichi Akahane ,  Noboru Tanabe ,  Yoshihito Sako

IPC分类号： G06F17/30 ,  H04L12/66 ,  H04L12/701 ,  H04L12/745 ,  G06F15/173

CPC分类号： H04L45/00 ,  H04L45/48 ,  H04L45/742

摘要： The present invention improves a network forwarding device, such as a router, in a computer network system. When an address to which a received packet is to be forwarded is searched for based on path information, a path search data structure is changed to the one in which, in a 2-branch tree search in which a destination address of the received packet is checked, one bit at a time beginning at a highest-order bit, p (p is an integer equal to or larger than 2) levels are combined into one 2P-branch tree to perform a search of the p levels of the 2-branch tree as a one-level search. This data structure speeds up path search processing.

摘要翻译： 本发明改进了计算机网络系统中的诸如路由器的网络转发设备。 当基于路径信息搜索要转发接收到的分组的地址时，将路径搜索数据结构改变为在其中所接收分组的目的地地址为2的分支树搜索中的路径搜索数据结构 检查，一个位从一个最高位开始，p（p是等于或大于2的整数）的级别被组合成一个2 分支树，以执行对p 2分支树作为一级搜索。 该数据结构加速了路径搜索处理。

公开(公告)号：US5752272A

公开(公告)日：1998-05-12

申请号：US729319

申请日：1996-10-15

申请人： Noboru Tanabe

发明人： Noboru Tanabe

IPC分类号： G06F12/08 ,  G06F9/38 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04

CPC分类号： G06F9/383 ,  G06F12/0862

摘要： A memory access control device capable of reducing the cache miss penalty and taking an advantage of the DRAM with a high transmission bandwidth. In this device, a high speed memory for storing block data read from the memory device is provided, Then, when an access request is received from the master device, data requested by the access request is returned from the high speed memory to the master device whenever the data requested by the access request are contained in the block data stored in the high speed memory. Otherwise new block data of a variable block length to be stored in the high speed memory is read from the memory device according to the access request received from the master device. The block data includes prefetch data which have a possibility for being requested by a next access request from the master device. The device may include an access continuity judging unit for judging an access continuity for memory accesses made by the master device such that the read out block length of the new block data is controlled according to the access continuity.

摘要翻译： 一种存储器访问控制装置，其能够降低高速缓存未命中并利用具有高传输带宽的DRAM的优点。 在该装置中，提供用于存储从存储装置读取的块数据的高速存储器，然后，当从主装置接收到访问请求时，由访问请求请求的数据从高速存储器返回到主装置 每当访问请求所请求的数据被包含在存储在高速存储器中的块数据中时。 否则，根据从主设备接收的访问请求，从存储设备读取要存储在高速存储器中的可变块长度的新块数据。 块数据包括预取数据，其具有可能被来自主设备的下一访问请求请求。 该设备可以包括访问连续性判断单元，用于判断由主设备进行的存储器访问的访问连续性，使得根据访问连续​​性来控制新的块数据的读出块长度。

公开(公告)号：US5467102A

公开(公告)日：1995-11-14

申请号：US411924

申请日：1995-03-28

申请人： Yoshinori Kuno ,  Noboru Tanabe ,  Koichi Hasebe

发明人： Yoshinori Kuno ,  Noboru Tanabe ,  Koichi Hasebe

IPC分类号： G06F15/02 ,  G06F1/16 ,  G06F3/147 ,  G09F9/00 ,  G09G3/02

CPC分类号： G06F1/1618 ,  G06F1/1643 ,  G06F1/1647 ,  G06F1/1677 ,  G06F1/1692 ,  G06F15/0283 ,  G06F3/147 ,  G06F2200/1614 ,  G09G2360/04 ,  Y10S345/901 ,  Y10S345/903

摘要： A portable display device capable of presenting a document in an easy to read format, in which a simultaneous display of different parts of the document in reasonable sizes can be made, by a simple operation of the device. The display device comprises a document memory for storing documents to be displayed, at least two display screens for displaying the documents stored in the document memory means, and a display control unit for controlling displays of the documents on the display screens to be in a linked mode in which the displays on the display screens are linked together and in a separate mode in which the displays on the display screens are independent from each other.

摘要翻译： 一种便携式显示设备，其能够以易于阅读的格式呈现文档，其中可以通过设备的简单操作来以合理的大小同时显示文档的不同部分。 显示装置包括用于存储要显示的文档的文档存储器，用于显示存储在文档存储装置中的文档的至少两个显示屏幕，以及显示控制单元，用于控制显示屏幕上的文档的显示，使其处于链接 显示屏幕上的显示器被链接在一起并且在显示屏幕上的显示器彼此独立的单独模式中的模式。