公开(公告)号：US4530280A

公开(公告)日：1985-07-23

申请号：US570492

申请日：1984-01-13

申请人： Nobuo Kaneko ,  Takeshi Takemoto ,  Hiroshi Yasuda

发明人： Nobuo Kaneko ,  Takeshi Takemoto ,  Hiroshi Yasuda

IPC分类号： B41J2/285 ,  B41J9/38 ,  B41J9/42 ,  B41J9/00

CPC分类号： B41J9/38

摘要： A printing hammer assembly for use in impact printers includes a printing hammer which has an impact surface and an armature and which is supported to be movable in a reciprocating manner along its longitudinal axis, a driving solenoid which drives to move the printing hammer forward when energized against the force of a coil spring which normally applies a biasing force to the printing hammer in the backward direction and a yoke leading a magnetic flux produced by said solenoid to the armature of printing hammer. A pair of magnets are disposed such that they are magnetically repulsive to each other with one of them fixed in position and the other movable over a predetermined distance thereby allowing to absorb the rebounding energy of the hammer when it returns to its home position.

摘要翻译： 用于冲击式打印机的打印锤组件包括具有冲击表面和电枢的打印锤，该打击锤被支撑成沿着其纵向轴线往复运动地运动，驱动螺线管驱动以在通电时向前移动打印锤 抵抗通常在打印锤向后方向施加偏置力的螺旋弹簧的力，以及将由所述螺线管产生的磁通量引导到打印锤的电枢的轭。 一对磁体被布置成使得它们彼此磁性排斥，其中一个固定在适当位置，另一个磁体可移动超过预定距离，从而允许当其回到其初始位置时吸收锤的回弹能量。

公开(公告)号：US08350297B2

公开(公告)日：2013-01-08

申请号：US12962118

申请日：2010-12-07

申请人： Nobuo Kaneko

发明人： Nobuo Kaneko

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66462

摘要： A compound semiconductor device is comprised of: a compound semiconductor layer including a first active layer and a second active layer forming a hetero junction with the first active layer so as to naturally generate a two-dimensional carrier gas channel in the first active layer along the hetero junction; a first electrode formed on the second active layer; a second electrode in ohmic contact with the first active layer and isolated from the first electrode; and a channel modifier for locally changing a part of the first active layer under the channel modifier into a normally-off state, the channel modifier being formed on the second active layer so as to enclose but be isolated from the first electrode and the second electrode.

摘要翻译： 化合物半导体器件包括：化合物半导体层，包括第一有源层和与第一有源层形成异质结的第二有源层，以便沿着沿着第一有源层的第一有源层自然地产生二维载气通道 异质结; 形成在所述第二有源层上的第一电极; 与所述第一有源层欧姆接触并与所述第一电极隔离的第二电极; 以及通道修正器，其用于将所述通道修饰器下方的所述第一有源层的一部分局部改变为常关状态，所述沟道改性剂形成在所述第二有源层上，以便包围但与所述第一电极和所述第二电极隔离 。

公开(公告)号：US07859021B2

公开(公告)日：2010-12-28

申请号：US12199323

申请日：2008-08-27

申请人： Nobuo Kaneko

发明人： Nobuo Kaneko

IPC分类号： H01L29/66

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/7787 ,  H01L29/808

摘要： A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current.

摘要翻译： HEMT型场效应半导体器件具有包括两层不同材料的主半导体区域，使得沿着两层之间的异质结产生二维电子气层。 源极和漏极放置在主半导体区域的主表面上的间隔位置。 在这些电极之间，栅电极通过p型金属氧化物半导体膜被接收在主半导体区域的主表面的凹部中，由此在电子气体层中通常产生耗尽区，最小的导通 电阻和栅极漏电流。

公开(公告)号：US4345953A

公开(公告)日：1982-08-24

申请号：US182312

申请日：1980-08-28

申请人： Nobuo Kaneko ,  Masaru Yamamoto

发明人： Nobuo Kaneko ,  Masaru Yamamoto

IPC分类号： C22C21/06 ,  C22C21/10

CPC分类号： C22C21/06 ,  C22C21/10

摘要： An aluminum-based die casting alloy for producing high strength, crack free die castings, comprising 4-8% Zn, 6-11% Mg, 0.05-0.45% Ti and/or Zr if desired, and the balance aluminum. In one embodiment, the die casting alloy may further comprise 0.3-2.0% Fe to prevent the die casting alloy in the molten state from eroding the gate and its neighborhood of a die during casting in the die.

摘要翻译： 一种用于生产高强度，无裂纹压铸件的铝基压铸合金，如果需要，包含4-8％的Zn，6-11％的Mg，0.05-0.45％的Ti和/或Zr，余量为铝。 在一个实施例中，压铸合金可以进一步包含0.3-2.0％的Fe，以防止熔融状态的压铸合金在模具中铸造期间侵蚀浇口及其邻近的模具。

公开(公告)号：US20110062438A1

公开(公告)日：2011-03-17

申请号：US12947088

申请日：2010-11-16

申请人： Nobuo Kaneko

发明人： Nobuo Kaneko

IPC分类号： H01L29/778

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/7787 ,  H01L29/808

摘要： A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current.

摘要翻译： HEMT型场效应半导体器件具有包括两层不同材料的主半导体区域，使得沿着两层之间的异质结产生二维电子气层。 源极和漏极放置在主半导体区域的主表面上的间隔位置。 在这些电极之间，栅电极通过p型金属氧化物半导体膜被接收在主半导体区域的主表面的凹部中，由此在电子气体层中通常产生耗尽区，最小的导通 电阻和栅极漏电流。

公开(公告)号：US20060138457A1

公开(公告)日：2006-06-29

申请号：US11357567

申请日：2006-02-17

申请人： Koji Otsuka ,  Nobuo Kaneko

发明人： Koji Otsuka ,  Nobuo Kaneko

IPC分类号： H01L29/739 ,  H01L31/0328 ,  H01L29/12 ,  H01L29/732

CPC分类号： H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/2003

摘要： A high electron mobility transistor is disclosed which has a double-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. The main semiconductor region, buffer region, and part of the substrate taper as they extend away from the rest of the substrate, providing slanting side surfaces. An electroconductive antileakage overlay covers these side surfaces via an electrically insulating overlay. Electrically coupled to the silicon substrate via a contact electrode, the antileakage overlay serves for reduction of current leakage along the side surfaces.

公开(公告)号：US20050110043A1

公开(公告)日：2005-05-26

申请号：US10988889

申请日：2004-11-15

申请人： Koji Otsuka ,  Masataka Yanagihara ,  Nobuo Kaneko

发明人： Koji Otsuka ,  Masataka Yanagihara ,  Nobuo Kaneko

IPC分类号： H01L29/26 ,  H01L21/205 ,  H01L21/335 ,  H01L21/338 ,  H01L29/20 ,  H01L29/778 ,  H01L29/812 ,  H01L29/739

CPC分类号： H01L29/7783 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/812

摘要： A substrate system of the kind having a buffer region interposed between a silicon substrate proper and a nitride semiconductor region in order to make up for a difference in linear expansion coefficient therebetween. Electrodes are formed on the nitride semiconductor layer or layers in order to provide HEMTs or MESFETs. The buffer region is a lamination of a multiplicity of buffer layers each comprising a first, a second, and a third buffer sublayer of nitride semiconductors, in that order from the silicon substrate proper toward the nitride semiconductor region. The three sublayers of each buffer layer contain aluminum in varying proportions including zero. The aluminum proportion of the third buffer sublayer is either zero or intermediate that of the first buffer sublayer and that of the second. The low aluminum proportion of the third buffer sublayer serves to prevent two-dimensional electron gas from generating in the buffer region and hence to make this region sufficiently high in resistance to inhibit current leakage from the HEMTs or MESFETs.

摘要翻译： 这种衬底系统具有介于硅衬底本体和氮化物半导体区域之间的缓冲区域，以补偿它们之间的线膨胀系数差。 为了提供HEMT或MESFET，在氮化物半导体层上形成电极。 缓冲区域是从硅衬底本身朝向氮化物半导体区域的顺序，分别包括氮化物半导体的第一，第二和第三缓冲子层的多个缓冲层的叠层。 每个缓冲层的三个子层含有不同比例的铝，包括零。 第三缓冲器子层的铝比例为零或与第一缓冲子层的第二缓冲层的铝比例为中等。 第三缓冲层的低铝比例用于防止在缓冲区域中产生二维电子气，从而使该区域具有足够高的电阻，以防止来自HEMT或MESFET的电流泄漏。

公开(公告)号：US08125004B2

公开(公告)日：2012-02-28

申请号：US12644907

申请日：2009-12-22

申请人： Nobuo Kaneko

发明人： Nobuo Kaneko

IPC分类号： H01L29/66

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/812

摘要： A heterojunction field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region and electrically coupled to the 2DEG layer. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film and insulating film, whereby a depletion zone is normally created in the 2DEG layer, making the device normally off. The p-type metal oxide semiconductor film of high hole concentration serves for the normally-off performance of the device with low gate leak current, and the insulating film for further reduction of gate leak current.

摘要翻译： 异质结场效应半导体器件具有包括两层不同材料的主半导体区域，使得沿着两层之间的异质结产生二维电子气层。 源极和漏极放置在主半导体区域的主表面上的间隔位置中并电耦合到2DEG层。 在这些电极之间，栅电极经由p型金属氧化物半导体膜和绝缘膜被接收在主半导体区域的主表面的凹部中，由此在2DEG层中通常产生耗尽区，使得器件正常 关闭 高空穴浓度的p型金属氧化物半导体膜用于具有低栅极漏电流的器件的常闭性能，以及用于进一步降低栅极漏电流的绝缘膜。

公开(公告)号：US07985987B2

公开(公告)日：2011-07-26

申请号：US12947088

申请日：2010-11-16

申请人： Nobuo Kaneko

发明人： Nobuo Kaneko

IPC分类号： H01L29/66

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/7787 ,  H01L29/808

摘要： A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film whereby a depletion zone is normally created in the electron gas layer, with a minimum of turn-on resistance and gate leak current.

摘要翻译： HEMT型场效应半导体器件具有包括两层不同材料的主半导体区域，使得沿着两层之间的异质结产生二维电子气层。 源极和漏极放置在主半导体区域的主表面上的间隔位置。 在这些电极之间，栅电极通过p型金属氧化物半导体膜被接收在主半导体区域的主表面的凹部中，由此在电子气体层中通常产生耗尽区，最小的导通 电阻和栅极漏电流。

公开(公告)号：US20100163930A1

公开(公告)日：2010-07-01

申请号：US12641637

申请日：2009-12-18

申请人： Nobuo Kaneko

发明人： Nobuo Kaneko

IPC分类号： H01L29/778 ,  H01L21/283

CPC分类号： H01L29/41758 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

摘要： An object of the present invention is to reduce on-state resistance and increases reliability in a semiconductor device having an electrode formed in a recessed structure.As illustrated in FIG. 1B, a first insulating layer 103 is formed. Then, as illustrated in FIG. 1C, a photolithography process is carried out to form a photoresist pattern 104. Subsequently, as illustrated in FIG. 1D, dry etching is applied to the first insulating layer 103. Then, as illustrated in FIG. 1E, a laminated semiconductor structure is etched. Next, in this state, wet etching is applied to the first insulating layer 103 as illustrated in FIG. 1F. Next, in this state, an electrode material 105 is formed on the entire exposed surface as illustrated in FIG. 1G. Finally, as illustrated in 1H, the photoresist pattern 104 is removed.

摘要翻译： 本发明的目的是降低导通电阻并增加具有形成在凹陷结构中的电极的半导体器件的可靠性。 如图1所示。 如图1B所示，形成第一绝缘层103。 然后，如图1所示。 如图1C所示，进行光刻工艺以形成光致抗蚀剂图案104。 如图1D所示，对第一绝缘层103施加干蚀刻。 如图1E所示，蚀刻层叠半导体结构。 接下来，在该状态下，如图1所示，对第一绝缘层103施加湿蚀刻。 1F。 接下来，在这种状态下，如图1所示，在整个暴露表面上形成电极材料105。 1G。 最后，如1H所示，去除光致抗蚀剂图案104。