公开(公告)号：US06661252B2

公开(公告)日：2003-12-09

申请号：US10190325

申请日：2002-07-03

申请人： Nobuo Nagano ,  Kazuhiko Onda ,  Junichi Somei

发明人： Nobuo Nagano ,  Kazuhiko Onda ,  Junichi Somei

IPC分类号： G11C700

CPC分类号： H04Q3/521

摘要： A matrix switch device comprises a semiconductor integrated circuit chip comprising a 2×2 matrix switch having two input terminals and two output terminals and an SPDT switch at a stage subsequent to the 2×2 matrix switch, the SPDT switch having two input terminals and one output terminal, wherein electrical connection is performed between one of the output terminals of the 2×2 matrix switch and one of the input terminals of the SPDT switch, and wherein the two input terminals and the other of said output terminals of the 2×2 matrix switch, and the other input terminal and the output terminal of the SPDT switch are led out of the semiconductor integrated circuit chip.

摘要翻译： 矩阵开关装置包括半导体集成电路芯片，其包括具有两个输入端子和两个输出端子的2x2矩阵开关和在2x2矩阵开关之后的阶段的SPDT开关，所述SPDT开关具有两个输入端子和一个输出端子，其中 在2x2矩阵开关的一个输出端子和SPDT开关的一个输入端子之间执行电连接，并且其中两个输入端子和2x2矩阵开关的另一个输出端子以及另一个输入端子 并且SPDT开关的输出端子被引出半导体集成电路芯片。

公开(公告)号：US20080197890A1

公开(公告)日：2008-08-21

申请号：US12068081

申请日：2008-02-01

申请人： Kei Yoshikawa ,  Ryusuke Shibata ,  Tokio Sawataishi ,  Nobuo Nagano ,  Koichi Iguchi

发明人： Kei Yoshikawa ,  Ryusuke Shibata ,  Tokio Sawataishi ,  Nobuo Nagano ,  Koichi Iguchi

IPC分类号： H02M11/00

CPC分类号： G11B7/13 ,  H03F3/087 ,  H03F3/45475 ,  H03F2203/45136 ,  H03G3/02 ,  H03G3/3084

摘要： A light receiving circuit according to the present invention includes a current control voltage generation circuit 10 outputting control voltages Vcont1 and Vcont2, a first current adjusting circuit 11 generating a first output current Io1 by regulating a first input current Ii1 depending on a voltage difference of the control voltages Vcont1 and Vcont2, the first input current Ii1 generated by adding a first reference current Ia1 and an input current Ipd, a second current adjusting circuit 12 generating a second output current Io2 by regulating a second reference current Ia2 depending on the voltage difference of the control voltages Vcont1 and Vcont2, and a current voltage conversion circuit 13 generating a first output voltage Vo1 by converting the first output current Io1 to voltage based on a first resistance Rf1 and generating a second output voltage Vo2 by converting the second output current Io2 to voltage based on a second resistance Rf2.

摘要翻译： 根据本发明的光接收电路包括输出控制电压Vcont1和Vcont2的电流控制电压产生电路10，第一电流调节电路11，其通过根据第一输入电流I 1调节第一输入电流Ii 1产生第一输出电流Io 控制电压Vcont1和Vcont2的电压差，通过将第一参考电流Ia 1和输入电流Ipd相加而产生的第一输入电流Ii 1，通过调节第二电流I 2产生第二输出电流Io 2的第二电流调节电路12 参考电流Ia 2取决于控制电压Vcont 1和Vcont 2的电压差，以及电流电压转换电路13，通过将第一输出电流Io 1转换为基于第一电阻Rf 1的电压来产生第一输出电压Vo 1 以及通过将第二输出电流Io 2转换为基于第二电阻Rf 2的电压来产生第二输出电压Vo 2。

公开(公告)号：US07714269B2

公开(公告)日：2010-05-11

申请号：US12068081

申请日：2008-02-01

申请人： Kei Yoshikawa ,  Ryusuke Shibata ,  Tokio Sawataishi ,  Nobuo Nagano ,  Koichi Iguchi

发明人： Kei Yoshikawa ,  Ryusuke Shibata ,  Tokio Sawataishi ,  Nobuo Nagano ,  Koichi Iguchi

IPC分类号： H01J40/14

CPC分类号： G11B7/13 ,  H03F3/087 ,  H03F3/45475 ,  H03F2203/45136 ,  H03G3/02 ,  H03G3/3084

摘要： A light receiving circuit according to the present invention includes a current control voltage generation circuit 10 outputting control voltages Vcont1 and Vcont2, a first current adjusting circuit 11 generating a first output current Io1 by regulating a first input current Ii1 depending on a voltage difference of the control voltages Vcont1 and Vcont2, the first input current Ii1 generated by adding a first reference current Ia1 and an input current Ipd, a second current adjusting circuit 12 generating a second output current Io2 by regulating a second reference current Ia2 depending on the voltage difference of the control voltages Vcont1 and Vcont2, and a current voltage conversion circuit 13 generating a first output voltage Vo1 by converting the first output current Io1 to voltage based on a first resistance Rf1 and generating a second output voltage Vo2 by converting the second output current Io2 to voltage based on a second resistance Rf2.

摘要翻译： 根据本发明的光接收电路包括输出控制电压Vcont1和Vcont2的电流控制电压产生电路10，第一电流调节电路11，其通过根据第一输入电流I i1的电压差来调节第一输入电流Ii1，产生第一输出电流Io 控制电压Vcont1和Vcont2，通过加上第一参考电流Ia1和输入电流Ipd产生的第一输入电流Ii1，通过根据电压差调节第二参考电流Ia2来产生第二输出电流Io2的第二电流调节电路 控制电压Vcont1和Vcont2以及电流电压转换电路13，通过将第一输出电流Io1转换为基于第一电阻Rf1的电压并产生第二输出电压Vo2，从而产生第一输出电压Vo1，通过将第二输出电流Io2转换为 基于第二电阻Rf2的电压。

公开(公告)号：US06467666B2

公开(公告)日：2002-10-22

申请号：US09870299

申请日：2001-05-30

申请人： Seiji Ichikawa ,  Tatsuo Tokue ,  Nobuo Nagano ,  Fumie Ogihara ,  Taku Sato

发明人： Seiji Ichikawa ,  Tatsuo Tokue ,  Nobuo Nagano ,  Fumie Ogihara ,  Taku Sato

IPC分类号： B65H2300

CPC分类号： H01L21/67092 ,  B28D5/0011 ,  H01L21/3043 ,  H01L21/78 ,  H05K1/0306 ,  H05K3/0052 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2203/1572 ,  H05K2203/302 ,  Y10T225/12 ,  Y10T225/325

摘要： A method of producing a semiconductor device of the present invention is applicable to a multilayer wafer for leadless chip carrier packages and breaks it on a package basis. The method begins with a step of forming a generally V-shaped groove in one major surfaces of the wafer in the direction of thickness of the wafer. A weak, cleaving portion is formed in the other major surface of the wafer in alignment with the groove. A cleaving force is exerted on the wafer to thereby form a break in the cleaving portion, so that the wafer is caused to break from the groove toward the cleaving portion in the direction of thickness of the wafer. The cleaving portion may be replaced with a strong, non-cleaving portion, in which case the break is formed in the interface between the non-cleaving portion and the wafer due to a difference in cleaving force.

摘要翻译： 本发明的半导体器件的制造方法可应用于无引线芯片载体封装的多层晶片，并以封装为基础将其破坏。 该方法开始于在晶片的一个主表面上沿晶片厚度方向形成大致V形槽的步骤。 在晶片的另一个主表面上与凹槽对准地形成弱的分离部分。 切割力施加在晶片上，从而在裂开部分形成断裂，从而使得晶片在晶片的厚度方向上从凹槽向分裂部分断裂。 切割部分可以用强的非分裂部分代替，在这种情况下，由于分裂力的差异，在非裂开部分和晶片之间的界面中形成断裂。