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公开(公告)号:US20120278651A1
公开(公告)日:2012-11-01
申请号:US13066976
申请日:2011-04-28
申请人: Naveen Muralimanohar , Doe Hyun Yoon , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
发明人: Naveen Muralimanohar , Doe Hyun Yoon , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
IPC分类号: G06F11/20
摘要: Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block.
摘要翻译: 本文的实施例涉及用于重新映射数据的方法。 在一个实施例中,确定第一存储器块是否有故障。 指针被存储到第一存储器块,并且当第一存储器块发生故障时,设置第一存储器块的指针标志。 先前存储在第一存储器块的数据被写入第二存储器块,其中指针指向第二存储器块的位置。
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公开(公告)号:US08151122B1
公开(公告)日:2012-04-03
申请号:US11773759
申请日:2007-07-05
IPC分类号: G06F1/00
CPC分类号: G06F1/26
摘要: In a method for managing power budgets among a plurality of electronic components having respective power budgets, at least part of the power budget of an electronic component that has failed is dynamically re-allocated to at least one of the other plurality of electronic components, to thereby increase performance of the plurality of electronic components.
摘要翻译: 在用于管理具有各自的功率预算的多个电子部件中的功率预算的方法中,已经故障的电子部件的功率预算的至少一部分被动态地重新分配给其他多个电子部件中的至少一个, 从而增加了多个电子部件的性能。
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3.
公开(公告)号:US08732368B1
公开(公告)日:2014-05-20
申请号:US11061959
申请日:2005-02-17
IPC分类号: G06F12/00
CPC分类号: G06F12/0862 , G06F9/5011 , Y02D10/13 , Y02D10/22
摘要: A processing system is provided including sharing a resource in a processor system for processing signals, the processor system having first and second conjoined-cores, and selecting the conjoined-core having control over the resource based on arbitration between the first and second conjoined-cores.
摘要翻译: 提供一种处理系统,包括在用于处理信号的处理器系统中共享资源,处理器系统具有第一和第二联结核,以及基于第一和第二联结核之间的仲裁来选择具有对资源的控制的联结核 。
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公开(公告)号:US08639968B2
公开(公告)日:2014-01-28
申请号:US13007741
申请日:2011-01-17
申请人: Doe Hyun Yoon , Naveen Muralimanohar , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
发明人: Doe Hyun Yoon , Naveen Muralimanohar , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
IPC分类号: G06F11/00
CPC分类号: G06F11/1438 , G06F11/1076 , G06F11/2056 , G06F11/2094
摘要: Systems, methods, and computer-readable and executable instructions are provided for computing system reliability. A method for computing system reliability can include storing, on one of a plurality of devices, a checkpoint of a current state associated with the one of the plurality of devices. The method may further include storing the checkpoint in an erasure-code group across the plurality of devices.
摘要翻译: 提供系统,方法和计算机可读和可执行指令来计算系统的可靠性。 用于计算系统可靠性的方法可以包括在多个设备中的一个设备上存储与所述多个设备中的一个设备相关联的当前状态的检查点。 该方法还可以包括将检查点存储在多个设备中的擦除代码组中。
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公开(公告)号:US07996839B2
公开(公告)日:2011-08-09
申请号:US10621067
申请日:2003-07-16
CPC分类号: G06F9/5044 , G06F9/5088
摘要: A computer system for maximizing system and individual job throughput includes a number of computer hardware processor cores that differ amongst themselves in at least in their respective resource requirements and processing capabilities. A monitor gathers performance metric information from each of the computer hardware processor cores that are specific to a particular run of application software then executing. Based on these metrics, a workload assignment mechanism assigns jobs to processor cores in order to maximize overall system throughput and the throughput of individual jobs.
摘要翻译: 用于最大化系统和单个作业吞吐量的计算机系统包括多个计算机硬件处理器核心,其至少在它们各自的资源需求和处理能力中彼此不同。 监视器从特定于特定应用软件运行的每个计算机硬件处理器核心收集性能指标信息,然后执行。 基于这些指标,工作负载分配机制将作业分配给处理器核心,以最大化整体系统吞吐量和单个作业的吞吐量。
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公开(公告)号:US07941698B1
公开(公告)日:2011-05-10
申请号:US12252144
申请日:2008-10-15
IPC分类号: G06F11/00
CPC分类号: G06F11/1641 , G06F11/1471 , G06F11/1497 , G06F11/1675 , G06F11/184 , G06F2201/805 , G06F2201/81 , G06F2201/845
摘要: Processor operating methods and integrated circuits are described. According to one embodiment, an integrated circuit includes a processor configured to execute a first application and to redundantly execute a second application while executing the first application, the first application being different from the second application. According to another embodiment, a processor operating method includes receiving a request to execute an application using a processor having a plurality of processor cores. The method also includes, in response to the receiving, determining whether the application should be executed redundantly or non-redundantly, non-redundantly executing the application using one processor core of the plurality if the determining comprises determining that the application should be executed non-redundantly, and redundantly executing the application using two or more processor cores of the plurality if the determining comprises determining that the application should be executed redundantly.
摘要翻译: 描述处理器操作方法和集成电路。 根据一个实施例,集成电路包括被配置为执行第一应用并且在执行第一应用时冗余地执行第二应用的处理器,所述第一应用与第二应用不同。 根据另一个实施例,处理器操作方法包括使用具有多个处理器核的处理器来接收执行应用的请求。 所述方法还包括:响应于所述接收,确定所述应用是否应该被冗余地执行或非冗余地执行,如果所述确定包括确定所述应用应该被执行,则非冗余地执行所述应用的多个处理器核心, 冗余地并冗余地执行应用程序,如果确定包括确定该应用程序应该被冗余执行,则使用多个的两个或多个处理器核心。
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公开(公告)号:US20100194470A1
公开(公告)日:2010-08-05
申请号:US12366234
申请日:2009-02-05
申请人: Matteo Monchiero , Jacob B. Leverich , Parthasarathy Ranganathan , Norman Paul Jouppi , Vanish Talwar
发明人: Matteo Monchiero , Jacob B. Leverich , Parthasarathy Ranganathan , Norman Paul Jouppi , Vanish Talwar
IPC分类号: H01L25/00
CPC分类号: H01L25/0657 , H01L23/36 , H01L25/18 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H03K19/0016 , H01L2924/00 , H01L2224/0401
摘要: An integrated circuit package includes a digital logic die disposed on a substrate; and an interposer die stacked vertically with the digital logic die on the substrate. The interposer die includes at least one vertical transistor configured to selectively provide electrical power to a portion of the digital logic die.
摘要翻译: 集成电路封装包括设置在基板上的数字逻辑管芯; 以及在基板上与数字逻辑管芯垂直堆叠的插入器管芯。 插入器管芯包括至少一个垂直晶体管,其构造成选择性地向数字逻辑管芯的一部分提供电功率。
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公开(公告)号:US09003247B2
公开(公告)日:2015-04-07
申请号:US13066976
申请日:2011-04-28
申请人: Naveen Muralimanohar , Doe Hyun Yoon , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
发明人: Naveen Muralimanohar , Doe Hyun Yoon , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
摘要: Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block.
摘要翻译: 本文的实施例涉及用于重新映射数据的方法。 在一个实施例中,确定第一存储器块是否有故障。 指针被存储到第一存储器块,并且当第一存储器块发生故障时,设置第一存储器块的指针标志。 先前存储在第一存储器块的数据被写入第二存储器块,其中指针指向第二存储器块的位置。
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9.
公开(公告)号:US09003168B1
公开(公告)日:2015-04-07
申请号:US11061696
申请日:2005-02-17
IPC分类号: G06F9/30 , G06F15/173
CPC分类号: G06F15/173 , G06F9/3891 , G06F13/1663 , Y02D10/14
摘要: A processing system is provided for processing signals in a processor system including first and second conjoined-cores, and sharing a single floating point unit or a single memory interconnection network port by the first and second conjoined-cores.
摘要翻译: 提供处理系统,用于在包括第一和第二联结核的处理器系统中处理信号,并且通过第一和第二联结核共享单个浮点单元或单个存储器互连网络端口。
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公开(公告)号:US20120272036A1
公开(公告)日:2012-10-25
申请号:US13092912
申请日:2011-04-23
申请人: Naveen Muralimanohar , Jichuan Chang , Parthasarathy Ranganathan , Doe Hyun Yoon , Norman Paul Jouppi
发明人: Naveen Muralimanohar , Jichuan Chang , Parthasarathy Ranganathan , Doe Hyun Yoon , Norman Paul Jouppi
IPC分类号: G06F12/06
CPC分类号: G06F12/0238 , G06F12/06 , G06F2212/7202 , G06F2212/7208 , Y02D10/13
摘要: An adaptive, memory system is provided. The adaptive memory system has a number of physical-memory devices and a memory controller that creates and maintains a logical address space to which the physical-memory devices and data-storage allocations are mapped, and through which mapping the memory controller matches static, dynamic, and dynamically-adjustable retention and resiliency characteristics of portions of the physical-memory devices with specified retention and resiliency characteristics specified for the data-storage allocations.
摘要翻译: 提供了一种自适应的存储系统。 自适应存储器系统具有多个物理存储器设备和存储器控制器,其创建并维护物理存储器件和数据存储器分配映射到的逻辑地址空间,并且存储器控制器通过映射将静态,动态 ,以及具有为数据存储分配指定的指定保留和弹性特性的物理存储器件的部分动态可调保留和弹性特性。
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