公开(公告)号：US10671548B2

公开(公告)日：2020-06-02

申请号：US15972990

申请日：2018-05-07

Applicant: Oracle International Corporation

Inventor： Darryl J. Gove

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/14 ,  G06F12/0875 ,  G06F12/0888

Abstract: In some embodiments, a memory initialization detection process includes detecting a read instruction of a program, where the read instruction addresses a particular memory location, and where data corresponding to the particular memory location is cached in a particular cache line of a memory cache. The memory initialization detection process further includes determining, based on metadata stored in the memory cache, that a section of the particular cache line does not store valid data of the program. The memory initialization detection process further includes obtaining validity data from the section of the particular cache line. The memory initialization detection process further includes determining, based on the validity data, whether the read instruction is authorized to proceed.

公开(公告)号：US20150046687A1

公开(公告)日：2015-02-12

申请号：US13960235

申请日：2013-08-06

Applicant: Oracle International Corporation

Inventor： Darryl J. Gove ,  David L. Weaver ,  Gerald Zuraski

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30043 ,  G06F9/3455 ,  G06F9/3824

Abstract: A processor having a streaming unit is disclosed. In one embodiment, a processor includes one or more execution units configured to execute instructions of a processor instruction set. The processor further includes a streaming unit configured to execute a first instruction of the processor instruction set, wherein executing the first instruction comprises the streaming unit loading a first data stream from a memory of a computer system responsive to execution of a first instruction. The first data stream comprises a plurality of data elements. The first instruction includes a first argument indicating a starting address of the first stream, a second argument indicating a stride between the data elements, and a third argument indicative of an ending address of the stream. The streaming unit is configured to output a second data stream corresponding to the first data stream.

Abstract translation: 公开了一种具有流传输单元的处理器。 在一个实施例中，处理器包括被配置为执行处理器指令集的指令的一个或多个执行单元。 所述处理器还包括被配置为执行所述处理器指令集的第一指令的流传输单元，其中执行所述第一指令包括所述流单元响应于执行第一指令而从计算机系统的存储器加载第一数据流。 第一数据流包括多个数据元素。 第一指令包括指示第一流的起始地址的第一参数，指示数据元素之间的步幅的第二参数和指示流的结束地址的第三参数。 流传输单元被配置为输出对应于第一数据流的第二数据流。

公开(公告)号：US20180253389A1

公开(公告)日：2018-09-06

申请号：US15972990

申请日：2018-05-07

Applicant: Oracle International Corporation

Inventor： Darryl J. Gove

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F12/1416 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0875 ,  G06F12/0888 ,  G06F12/1425 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/466 ,  G06F2212/60

Abstract: In some embodiments, a memory initialization detection process includes detecting a read instruction of a program, where the read instruction addresses a particular memory location, and where data corresponding to the particular memory location is cached in a particular cache line of a memory cache. The memory initialization detection process further includes determining, based on metadata stored in the memory cache, that a section of the particular cache line does not store valid data of the program. The memory initialization detection process further includes obtaining validity data from the section of the particular cache line. The memory initialization detection process further includes determining, based on the validity data, whether the read instruction is authorized to proceed.

公开(公告)号：US09817762B2

公开(公告)日：2017-11-14

申请号：US14282771

申请日：2014-05-20

Applicant: Oracle International Corporation

Inventor： Sanjiv Kapil ,  Darryl J. Gove

IPC: G06F12/0862 ,  G06F12/1027 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/6028 ,  G06F2212/681

Abstract: The disclosed embodiments relate to a computing system that facilitates performing prefetching for scatter/gather operations. During operation, the system receives a scatter/gather prefetch instruction at a processor core, wherein the scatter/gather prefetch instruction specifies a virtual base address, and a plurality of offsets. Next, the system performs a lookup in a translation-lookaside buffer (TLB) using the virtual base address to obtain a physical base address that identifies a physical page for the base address. The system then sends the physical base address and the plurality of offsets to a cache. This enables the cache to perform prefetching operations for the scatter/gather instruction by adding the physical base address to the plurality of offsets to produce a plurality of physical addresses, and then prefetching cache lines for the plurality of physical addresses into the cache.

公开(公告)号：US20150046650A1

公开(公告)日：2015-02-12

申请号：US13960150

申请日：2013-08-06

Applicant: Oracle International Corporation

Inventor： Darryl J. Gove ,  David L. Weaver

IPC: G06F12/08

CPC classification number: G06F12/0813 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/383 ,  G06F9/3877 ,  G06F9/3897 ,  G06F12/0804

Abstract: A processor having a streaming unit is disclosed. In one embodiment, a processor includes a streaming unit configured to load one or more input data streams from a memory coupled to the processor. The streaming unit includes an internal network having a plurality of queues configured to store streams of data. The streaming unit further includes a plurality of operations circuits configured to perform operations on the streams of data. The streaming unit is software programmable to operatively couple two or more of the plurality of operations circuits together via one or more of the plurality of queues. The operations circuits may perform operations on multiple streams of data, resulting in corresponding output streams of data.

Abstract translation: 公开了一种具有流传输单元的处理器。 在一个实施例中，处理器包括被配置为从耦合到处理器的存储器加载一个或多个输入数据流的流传输单元。 流传输单元包括内部网络，其具有被配置为存储数据流的多个队列。 流式传输单元还包括多个操作电路，被配置为对数据流执行操作。 流式传输单元是软件可编程的，以通过多个队列中的一个或多个可操作地将多个操作电路中的两个或更多个耦合到一起。 操作电路可以对多个数据流执行操作，从而产生相应的输出数据流。

公开(公告)号：US09965402B2

公开(公告)日：2018-05-08

申请号：US14868308

申请日：2015-09-28

Applicant: Oracle International Corporation

Inventor： Darryl J. Gove

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F12/1416 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0875 ,  G06F12/0888 ,  G06F12/1425 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/466 ,  G06F2212/60

Abstract: In some embodiments, a memory initialization detection process includes detecting a read instruction of a program, where the read instruction addresses a particular memory location, and where data corresponding to the particular memory location is cached in a particular cache line of a memory cache. The memory initialization detection process further includes determining, based on metadata stored in the memory cache, that a section of the particular cache line does not store valid data of the program. The memory initialization detection process further includes obtaining validity data from the section of the particular cache line. The memory initialization detection process further includes determining, based on the validity data, whether the read instruction is authorized to proceed.

公开(公告)号：US20170091122A1

公开(公告)日：2017-03-30

申请号：US14868308

申请日：2015-09-28

Applicant: Oracle International Corporation

Inventor： Darryl J. Gove

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F12/1416 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0875 ,  G06F12/0888 ,  G06F12/1425 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/466 ,  G06F2212/60

Abstract: In some embodiments, a memory initialization detection process includes detecting a read instruction of a program, where the read instruction addresses a particular memory location, and where data corresponding to the particular memory location is cached in a particular cache line of a memory cache. The memory initialization detection process further includes determining, based on metadata stored in the memory cache, that a section of the particular cache line does not store valid data of the program. The memory initialization detection process further includes obtaining validity data from the section of the particular cache line. The memory initialization detection process further includes determining, based on the validity data, whether the read instruction is authorized to proceed.

公开(公告)号：US20150339233A1

公开(公告)日：2015-11-26

申请号：US14282771

申请日：2014-05-20

Applicant: Oracle International Corporation

Inventor： Sanjiv Kapil ,  Darryl J. Gove

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/6028 ,  G06F2212/681

Abstract: The disclosed embodiments relate to a computing system that facilitates performing prefetching for scatter/gather operations. During operation, the system receives a scatter/gather prefetch instruction at a processor core, wherein the scatter/gather prefetch instruction specifies a virtual base address, and a plurality of offsets. Next, the system performs a lookup in a translation-lookaside buffer (TLB) using the virtual base address to obtain a physical base address that identifies a physical page for the base address. The system then sends the physical base address and the plurality of offsets to a cache. This enables the cache to perform prefetching operations for the scatter/gather instruction by adding the physical base address to the plurality of offsets to produce a plurality of physical addresses, and then prefetching cache lines for the plurality of physical addresses into the cache.

Abstract translation: 所公开的实施例涉及有助于执行分散/收集操作的预取的计算系统。 在操作期间，系统在处理器核心处接收分散/收集预取指令，其中分散/收集预取指令指定虚拟基地址和多个偏移量。 接下来，系统使用虚拟基地址在翻译后备缓冲器（TLB）中执行查找，以获得识别基地址的物理页面的物理基址。 然后，系统将物理基地址和多个偏移发送到高速缓存。 这使得高速缓存能够通过将物理基址添加到多个偏移量来产生多个物理地址，然后将多个物理地址的高速缓存行预取到高速缓存中来执行分散/收集指令的预取操作。

公开(公告)号：US09043559B2

公开(公告)日：2015-05-26

申请号：US13658789

申请日：2012-10-23

Applicant: Oracle International Corporation

Inventor： Zoran Radovic ,  Darryl J. Gove

IPC: G06F12/00 ,  G06F12/16

CPC classification number: G06F12/16 ,  G06F11/00

Abstract: Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory operation in response to a command. Examples of block memory operations may include copy, clear, move, and/or compress operations. In one embodiment, the copy engine is configured to handle version information associated with the block memory operation based on the command. The one or more operations may include operating on data in a cache and/or modifying entries in a memory. In one embodiment, the copy engine is configured to compare version information in the command with stored version information. The copy engine may overwrite or preserve version information based on the command. The copy engine may be a coprocessing element. The copy engine may be configured to maintain coherency with other copy engines and/or processing elements.

Abstract translation: 使用复制引擎处理版本信息的技术。 在一个实施例中，一种装置包括配置成响应于命令执行与块存储器操作相关联的一个或多个操作的复制引擎。 块存储器操作的示例可以包括复制，清除，移动和/或压缩操作。 在一个实施例中，复制引擎被配置为基于该命令来处理与块存储器操作相关联的版本信息。 一个或多个操作可以包括对缓存中的数据进行操作和/或修改存储器中的条目。 在一个实施例中，复制引擎被配置为将命令中的版本信息与存储的版本信息进行比较。 复制引擎可以根据命令覆盖或保留版本信息。 复制引擎可以是协处理元件。 复制引擎可以被配置为保持与其他复制引擎和/或处理元件的一致性。

公开(公告)号：US20140115283A1

公开(公告)日：2014-04-24

申请号：US13658789

申请日：2012-10-23

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Zoran Radovic ,  Darryl J. Gove

IPC: G06F12/16

CPC classification number: G06F12/16 ,  G06F11/00

Abstract: Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory operation in response to a command. Examples of block memory operations may include copy, clear, move, and/or compress operations. In one embodiment, the copy engine is configured to handle version information associated with the block memory operation based on the command. The one or more operations may include operating on data in a cache and/or modifying entries in a memory. In one embodiment, the copy engine is configured to compare version information in the command with stored version information. The copy engine may overwrite or preserve version information based on the command. The copy engine may be a coprocessing element. The copy engine may be configured to maintain coherency with other copy engines and/or processing elements.

Abstract translation: 使用复制引擎处理版本信息的技术。 在一个实施例中，一种装置包括配置成响应于命令执行与块存储器操作相关联的一个或多个操作的复制引擎。 块存储器操作的示例可以包括复制，清除，移动和/或压缩操作。 在一个实施例中，复制引擎被配置为基于该命令来处理与块存储器操作相关联的版本信息。 一个或多个操作可以包括对缓存中的数据进行操作和/或修改存储器中的条目。 在一个实施例中，复制引擎被配置为将命令中的版本信息与存储的版本信息进行比较。 拷贝引擎可以根据命令覆盖或保留版本信息。 复制引擎可以是协处理元件。 复制引擎可以被配置为保持与其他复制引擎和/或处理元件的一致性。