INTER-PROCESSOR BUS LINK AND SWITCH CHIP FAILURE RECOVERY
    3.
    发明申请
    INTER-PROCESSOR BUS LINK AND SWITCH CHIP FAILURE RECOVERY 有权
    处理器总线链路和切换芯片故障恢复

    公开(公告)号:US20160210255A1

    公开(公告)日:2016-07-21

    申请号:US14598640

    申请日:2015-01-16

    CPC classification number: G06F13/4022 G06F11/221 H04L12/00 H04L12/4625

    Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.

    Abstract translation: 公开了一种系统,其中系统可以包括多个总线开关和多个处理器。 每个处理器可以耦合到每个总线开关。 每个处理器可以被配置为启动数据到给定总线开关的传输,并检测到给定总线开关的相应链路是否不可操作。 响应于检测到不可操作的链接到第一总线交换机,给定处理器可以进一步被配置为经由至少第二总线交换机向至少一个其他处理器发送通知消息,并且从一个第二总线交换机去除对应于不可操作链路的路由信息 首先注册 响应于从给定处理器接收到通知消息,至少一个其他处理器可以被配置为从第二寄存器去除对应于不可操作链路的附加路由信息。

    CACHE PROBE REQUEST TO OPTIMIZE I/O DIRECTED CACHING
    7.
    发明申请
    CACHE PROBE REQUEST TO OPTIMIZE I/O DIRECTED CACHING 有权
    高速缓存请求优化I / O方向缓存

    公开(公告)号:US20150278092A1

    公开(公告)日:2015-10-01

    申请号:US14675351

    申请日:2015-03-31

    CPC classification number: G06F9/5016 G06F12/0813 G06F12/0822 G06F12/0831

    Abstract: A method and system for allocating data streams that includes receiving, at an allocator, a data stream. The data stream includes a memory address and data associated with the memory address. The method also includes examining, by the allocator, the data stream to make a determination that the data stream is a soft allocating data stream, and then sending, from the allocator based on the determination, a plurality of write probes to a plurality of caches, wherein each write probe of the plurality of write probes includes at least part of the memory address. Additionally, the method includes receiving, at the allocator in response to a write probe of the plurality of write probes, a cache line present acknowledgement from a cache of the plurality of caches, and directing, by the allocator in response to the cache line present acknowledgement, the data of the data stream to the cache.

    Abstract translation: 一种用于分配数据流的方法和系统,包括在分配器处接收数据流。 数据流包括与存储器地址相关联的存储器地址和数据。 该方法还包括由分配器检查数据流以确定数据流是软分配数据流,然后基于确定从分配器发送多个写入探测到多个高速缓存 ,其中所述多个写入探针中的每个写入探针包括所述存储器地址的至少一部分。 另外,该方法包括在分配器处响应于多个写入探测器的写入探针而从多个高速缓存的高速缓存中接收高速缓存行当前确认,并且响应于存在的高速缓存行指示分配器 确认数据流到缓存的数据。

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