公开(公告)号：US10225196B2

公开(公告)日：2019-03-05

申请号：US14765841

申请日：2013-02-15

申请人： Roy Shor ,  Ori Goren ,  Avraham Horn ,  John Vaglica ,  Tuongvu Nguyen

发明人： Roy Shor ,  Ori Goren ,  Avraham Horn ,  John Vaglica ,  Tuongvu Nguyen

IPC分类号： H04L12/833 ,  H04L29/08 ,  H04W72/04

摘要： A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.

公开(公告)号：US20070088889A1

公开(公告)日：2007-04-19

申请号：US11610956

申请日：2006-12-14

申请人： Arnaldo Cruz ,  John Vaglica ,  William Moyer ,  Tuongvu Nguyen

发明人： Arnaldo Cruz ,  John Vaglica ,  William Moyer ,  Tuongvu Nguyen

IPC分类号： G06F13/24

CPC分类号： G06F13/385 ,  G06F13/24 ,  G06F2213/0042

摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

摘要翻译： 需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。 可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。 在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。 电路（402,417,480）可用于为诸如中断的附加信号提供转向。 其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

公开(公告)号：US20050080966A1

公开(公告)日：2005-04-14

申请号：US10682558

申请日：2003-10-09

申请人： Arnaldo Cruz ,  John Vaglica ,  William Moyer ,  Tuongvu Nguyen

发明人： Arnaldo Cruz ,  John Vaglica ,  William Moyer ,  Tuongvu Nguyen

IPC分类号： G06F13/14 ,  G06F13/24 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F13/24 ,  G06F2213/0042

摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

摘要翻译： 需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。 可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。 在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。 电路（402,417,480）可用于为诸如中断的附加信号提供转向。 其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

公开(公告)号：US20150028948A1

公开(公告)日：2015-01-29

申请号：US13953597

申请日：2013-07-29

申请人： Joseph Staudinger ,  Paul Hart ,  Ramanujam Srinidhi Embar ,  John Vaglica

发明人： Joseph Staudinger ,  Paul Hart ,  Ramanujam Srinidhi Embar ,  John Vaglica

IPC分类号： H03F3/217

CPC分类号： H03F3/2171 ,  H03F1/0288

摘要： A device includes a Doherty amplifier. The Doherty amplifier has a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a resistive switch having a first terminal connected to the peaking path and a second terminal connected to a voltage reference, and a controller configured to set the resistive switch to a first resistance value when a power input of the Doherty amplifier is below a threshold and to a second resistance value when the power input of the Doherty amplifier is above the threshold.

摘要翻译： 一个器件包括一个Doherty放大器。 Doherty放大器具有载波路径和峰值路径。 多赫蒂放大器包括被配置为放大从载波路径接收的信号的载波放大器和配置成放大从峰值路径接收的信号的峰值放大器。 该装置包括具有连接到峰化路径的第一端子和连接到电压基准的第二端子的电阻开关，以及控制器，其被配置为当Doherty放大器的功率输入低于一个时，将该电阻开关设置为第一电阻值 当Doherty放大器的功率输入高于阈值时，阈值和第二电阻值。

公开(公告)号：US20050265507A1

公开(公告)日：2005-12-01

申请号：US10747844

申请日：2003-12-29

申请人： Charbel Khawand ,  Jianping Tao ,  John Vaglica

发明人： Charbel Khawand ,  Jianping Tao ,  John Vaglica

IPC分类号： H04J3/06 ,  H04L7/00 ,  H04L23/00

CPC分类号： G06F9/542

摘要： The invention concerns a method (500) for employing adaptive event codes. The method includes the steps of generating (512) at least one adaptive event code in which the adaptive event code corresponds to a preexisting event code, storing (514) the adaptive event code in at least one table (154, 156), running (516) the table in which the adaptive event codes are at least initially disabled and enabling (522) the adaptive event code in response to a system event in which the preexisting event code that corresponds to the enabled adaptive event code is executed (526). The method can further include the step of ignoring (518) the adaptive event codes during the running step when the adaptive event codes are disabled.

摘要翻译： 本发明涉及一种采用自适应事件代码的方法（500）。 该方法包括以下步骤：产生（512）至少一个自适应事件代码，其中自适应事件代码对应于预先存在的事件代码，将自适应事件代码存储在至少一个表（154,156）中，运行（ 516）响应于其中执行与启用的自适应事件代码相对应的预先存在的事件代码的系统事件，启用（522）自适应事件代码（526），其中自适应事件代码至少被初始禁用的表（526）。 该方法还可以包括当禁用自适应事件代码时在运行步骤期间忽略（518）自适应事件代码的步骤。

公开(公告)号：US20050080961A1

公开(公告)日：2005-04-14

申请号：US10682571

申请日：2003-10-09

申请人： Ryan Bedwell ,  Arnaldo Cruz ,  John Vaglica ,  William Moyer

发明人： Ryan Bedwell ,  Arnaldo Cruz ,  John Vaglica ,  William Moyer

IPC分类号： G06F20060101 ,  G06F13/36 ,  G06F13/364

CPC分类号： G06F13/364

摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

公开(公告)号：US20100325327A1

公开(公告)日：2010-12-23

申请号：US12486387

申请日：2009-06-17

申请人： Bryan D. Marietta ,  Jaideep Dastidar ,  John Vaglica ,  Mihir A. Pandya

发明人： Bryan D. Marietta ,  Jaideep Dastidar ,  John Vaglica ,  Mihir A. Pandya

IPC分类号： G06F13/36

CPC分类号： G06F13/1642

摘要： A system includes a plurality of sources to provide information access requests. An arbiter includes an assignment module to associate a first access request from the first source to one of the plurality of arbitration slots based upon assignment information at a storage location, and a dispatch module to determine one request of a plurality of requests received at the plurality of sources to be dispatched to a resource, memory controller by a dispatch module.

摘要翻译： 系统包括提供信息访问请求的多个源。 仲裁器包括分配模块，用于基于存储位置处的分配信息将来自第一源的第一接入请求与多个仲裁时隙中的一个相关联，以及调度模块，用于确定在多个仲裁时隙中接收的多个请求的一个请求 要发送到资源的源，由调度模块的内存控制器。

公开(公告)号：US20060195721A1

公开(公告)日：2006-08-31

申请号：US11065898

申请日：2005-02-25

申请人： William Moyer ,  John Vaglica

发明人： William Moyer ,  John Vaglica

IPC分类号： G06F11/00

CPC分类号： G06F11/3648

摘要： A data processing system (10) has a system debug module (19) coupled to a processor (12) for performing system debug functions. Located within the system, and preferably within the processor, is debug circuitry (32) that selectively provides debug information related to the processor. The circuitry identifies which of a plurality of registers (26) is sourcing the debug information. A user-determinable enable and disable mechanism that is correlated to some or all of the registers sourcing the debug information specifies whether to enable or disable the providing of the debug information. In one form a single bit functions as the mechanism for each correlated register. Debug operations including breakpoints, tracing, watchpoints, halting, event counting and others are qualified to enhance system debug. The registers may be included in a programmer's model and can be compliant with one or more industry debug related standards.

摘要翻译： 数据处理系统（10）具有耦合到处理器（12）的用于执行系统调试功能的系统调试模块（19）。 位于系统内，并且优选地在处理器内的是调试电路（32），其选择性地提供与处理器相关的调试信息。 电路识别多个寄存器（26）中的哪一个正在提供调试信息。 与源自调试信息的一些或所有寄存器相关联的用户可确定的启用和禁用机制指定是否启用或禁用提供调试信息。 在一种形式中，单个位用作每个相关寄存器的机制。 包括断点，跟踪，观察点，停止，事件计数等的调试操作有资格加强系统调试。 寄存器可能包含在程序员模型中，并且可以符合一个或多个行业调试相关标准。

公开(公告)号：US20050215227A1

公开(公告)日：2005-09-29

申请号：US10806498

申请日：2004-03-23

申请人： Mieu Vu ,  Christopher Chun ,  Arthur Goldberg ,  David Hayes ,  Charbel Khawand ,  Jianping Tao ,  John Vaglica

发明人： Mieu Vu ,  Christopher Chun ,  Arthur Goldberg ,  David Hayes ,  Charbel Khawand ,  Jianping Tao ,  John Vaglica

IPC分类号： H04B1/16 ,  H04B1/38

CPC分类号： H04W52/0277 ,  Y02D70/00

摘要： A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system (10) has power control circuitry (52) which may be used to control power usage in data processing system (10). Power mode select circuitry (84) may be used to select a power mode. Depending upon the power mode selected, power control circuitry (52) may use a cascaded approach to selecting which portions of data processing system (10) will be powered down, and thus how deeply data processing system (10) will be powered down.

摘要翻译： 提供一种用于进入低功率模式的方法和装置。 在一个实施例中，数据处理系统（10）具有功率控制电路（52），其可用于控制数据处理系统（10）中的功率使用。 电源模式选择电路（84）可用于选择电源模式。 根据所选择的功率模式，功率控制电路（52）可以使用级联的方法来选择数据处理系统（10）的哪些部分将被掉电，并且因此数据处理系统（10）将被断电多深。

公开(公告)号：US09136804B2

公开(公告)日：2015-09-15

申请号：US13953597

申请日：2013-07-29

申请人： Joseph Staudinger ,  Paul Hart ,  Ramanujam Srinidhi Embar ,  John Vaglica

发明人： Joseph Staudinger ,  Paul Hart ,  Ramanujam Srinidhi Embar ,  John Vaglica

IPC分类号： H03F1/07 ,  H03F3/217

CPC分类号： H03F3/2171 ,  H03F1/0288

摘要： A device includes a Doherty amplifier. The Doherty amplifier has a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a resistive switch having a first terminal connected to the peaking path and a second terminal connected to a voltage reference, and a controller configured to set the resistive switch to a first resistance value when a power input of the Doherty amplifier is below a threshold and to a second resistance value when the power input of the Doherty amplifier is above the threshold.

摘要翻译： 一个器件包括一个Doherty放大器。 Doherty放大器具有载波路径和峰值路径。 多赫蒂放大器包括被配置为放大从载波路径接收的信号的载波放大器和配置成放大从峰值路径接收的信号的峰值放大器。 该装置包括具有连接到峰化路径的第一端子和连接到电压基准的第二端子的电阻开关，以及控制器，其被配置为当Doherty放大器的功率输入低于一个时，将该电阻开关设置为第一电阻值 当Doherty放大器的功率输入高于阈值时，阈值和第二电阻值。