公开(公告)号：US20060105563A1

公开(公告)日：2006-05-18

申请号：US10989937

申请日：2004-11-15

申请人： Omar Zia ,  Hsiao-Hui Chen ,  Lawrence Gunn

发明人： Omar Zia ,  Hsiao-Hui Chen ,  Lawrence Gunn

IPC分类号： H01L21/4763 ,  H01L21/76 ,  H01L21/00

CPC分类号： H01L23/48 ,  G02B6/132 ,  H01L21/84 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding dishing above the semiconductor device during chemical mechanical polishing. The dielectric that is above the semiconductor device and inside the guardian is etched to form an opening that receives one of an optical fiber, an electromagnetic signal source, or an electromagnetic signal load. The remaining dielectric is in layers that are of substantially uniform thickness. The guardian is built up in layers that are part of a normal integrated circuit process. These include contact layers, via layers, and interconnect layers.

摘要翻译： 半导体器件形成为集成电路的一部分。 形成在有源半导体层中的半导体器件被保护器包围，该保护器提供抵抗污染物的扩散阻挡层，并且还提供辅助以避免在化学机械抛光期间半导体器件上方的凹陷。 蚀刻在半导体器件上方和保护器内部的电介质，以形成接收光纤，电磁信号源或电磁信号负载之一的开口。 剩余的电介质是厚度基本均匀的层。 监护人建立在正常集成电路过程的一部分。 这些包括接触层，通孔层和互连层。

公开(公告)号：US07309628B2

公开(公告)日：2007-12-18

申请号：US10989937

申请日：2004-11-15

申请人： Omar Zia ,  Hsiao-Hui Chen ,  Lawrence Cary Gunn, III

发明人： Omar Zia ,  Hsiao-Hui Chen ,  Lawrence Cary Gunn, III

IPC分类号： H01L21/8238

CPC分类号： H01L23/48 ,  G02B6/132 ,  H01L21/84 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding dishing above the semiconductor device during chemical mechanical polishing. The dielectric that is above the semiconductor device and inside the guardian is etched to form an opening that receives one of an optical fiber, an electromagnetic signal source, or an electromagnetic signal load. The remaining dielectric is in layers that are of substantially uniform thickness. The guardian is built up in layers that are part of a normal integrated circuit process. These include contact layers, via layers, and interconnect layers.

摘要翻译： 半导体器件形成为集成电路的一部分。 形成在有源半导体层中的半导体器件被保护器包围，该保护器提供抵抗污染物的扩散阻挡层，并且还提供辅助以避免在化学机械抛光期间半导体器件上方的凹陷。 蚀刻在半导体器件上方和保护器内部的电介质，以形成接收光纤，电磁信号源或电磁信号负载之一的开口。 剩余的电介质是厚度基本均匀的层。 监护人建立在正常集成电路过程的一部分。 这些包括接触层，通孔层和互连层。

公开(公告)号：US20060105488A1

公开(公告)日：2006-05-18

申请号：US10988963

申请日：2004-11-15

申请人： Omar Zia ,  Nigel Cave ,  Lawrence Gunn

发明人： Omar Zia ,  Nigel Cave ,  Lawrence Gunn

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L27/0617 ,  H01L21/84

摘要： A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately optimized. The transistor has a salicide for source/drain contacts. During this process, a salicide block is used over the waveguide to prevent salicide formation in unwanted areas of the waveguide. The depth of the trench for the waveguide can be lower than that of the trench for the transistor isolation. Trench isolation depth can be set by an etch stop region that can be either a thin oxide layer or a buffer layer that is selectively etchable with respect to the top semiconductor layer and that can be used as a seed layer for growing the top semiconductor layer.

摘要翻译： 半导体结构在同一集成电路上具有波导晶体管。 一种沟槽隔离技术用于限定晶体管区域，另一种用于优化波导的横向边界。 波导和晶体管都具有可以单独优化的具有衬垫的沟槽。 晶体管具有用于源/漏触点的自对准硅。 在该过程中，在波导上使用自对准硅化物块以防止波导的不需要的区域中的自对准硅化物形成。 用于波导的沟槽的深度可以低于用于晶体管隔离的沟槽的深度。 沟槽隔离深度可以通过可以是相对于顶部半导体层可选择性蚀刻的薄氧化物层或缓冲层的蚀刻停止区域来设置，并且可以用作用于生长顶部半导体层的种子层。

公开(公告)号：US20060105508A1

公开(公告)日：2006-05-18

申请号：US10989947

申请日：2004-11-15

申请人： Omar Zia ,  Lawrence Gunn

发明人： Omar Zia ,  Lawrence Gunn

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A method for integrating first and second type devices on a semiconductor substrate includes forming openings within an active semiconductor layer of a dual semiconductor-on-insulator in first and second regions of the semiconductor substrate. First and second non-MOS transistor device implant regions are formed within portions of an intermediate semiconductor layer underlying first and second openings, respectively, in a first device portion, filled with a fill material and planarized. A top surface portion of the active semiconductor layer disposed in-between the first and second openings is exposed, first and second low dose non-MOS transistor device well regions are formed in respective first and second portions of the intermediate semiconductor layer underlying a region in-between the first and second openings. The method further includes forming a salicide blocking layer, forming first and second contact vias within the fill material of the first and second openings, respectively, exposing a portion of the underlying intermediate semiconductor layer, forming first and second non-MOS transistor device contact regions in exposed portions of the intermediate semiconductor layer, and saliciding the semiconductor substrate, the salicide blocking layer preventing salicidation of the first and second low dose non-MOS transistor device well regions.

摘要翻译： 一种用于在半导体衬底上集成第一和第二类型器件的方法包括在半导体衬底的第一和第二区域中的双绝缘绝缘体半导体有源半导体层内形成开口。 第一和第二非MOS晶体管器件注入区分别形成在填充有填充材料并且被平坦化的第一器件部分中的分别位于第一和第二开口下方的中间半导体层的部分内。 设置在第一和第二开口之间的有源半导体层的顶表面部分被暴露，第一和第二低剂量非MOS晶体管器件阱区域形成在中间半导体层的相应的第一和第二部分中， - 在第一和第二开口之间。 该方法还包括形成自对准硅化物阻挡层，分别在第一和第二开口的填充材料内形成第一和第二接触通孔，暴露下面的中间半导体层的一部分，形成第一和第二非MOS晶体管器件接触区域 在中间半导体层的露出部分中，对半导体衬底进行水杨酸化处理，防止第一和第二低剂量非MOS晶体管器件阱区域的水化作用。

公开(公告)号：US20060105509A1

公开(公告)日：2006-05-18

申请号：US10990215

申请日：2004-11-15

申请人： Omar Zia ,  Lawrence Gunn

发明人： Omar Zia ,  Lawrence Gunn

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0629

摘要： A method of integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate includes forming openings within an active semiconductor layer in first and second regions of a semiconductor substrate. The first region corresponds to a non-MOS transistor device portion and the second region corresponds to a CMOS electronic device portion. The openings are formed using a dual trench process, forming openings or shallow trenches in the non-MOS transistor device portion to a first depth, and openings in the CMOS electronic device portion to a second depth greater than the first depth. The method further includes forming first and second non-MOS transistor device implant regions within the active semiconductor layer underlying the shallow trenches in the non-MOS transistor device portion, forming first and second low dose non-MOS transistor device well regions in the active semiconductor layer disposed in-between the first and second shallow trenches, forming high dose non-MOS transistor device connectivity regions, forming a salicide blocking layer overlying at least the first and second low dose non-MOS transistor device well regions, forming first and second non-MOS transistor device contact regions, and saliciding the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the first and second low dose non-MOS transistor device well regions.

摘要翻译： 在半导体衬底上集成非MOS晶体管器件和CMOS电子器件的方法包括在半导体衬底的第一和第二区域中的有源半导体层内形成开口。 第一区域对应于非MOS晶体管器件部分，第二区域对应于CMOS电子器件部分。 使用双沟槽工艺形成开口，在非MOS晶体管器件部分中形成第一深度的开口或浅沟槽，并将CMOS电子器件部分中的开口形成为大于第一深度的第二深度。 该方法还包括在非MOS晶体管器件部分中的浅沟槽下面的有源半导体层内形成第一和第二非MOS晶体管器件注入区域，在有源半导体中形成第一和第二低剂量非MOS晶体管器件阱区域 形成高剂量非MOS晶体管器件连通性区域，形成至少覆盖第一和第二低剂量非MOS晶体管器件阱区域的自对准硅化物阻挡层，形成第一和第二非MOS晶体管器件连接区域， -MOS晶体管器件接触区域，并对半导体衬底进行水蚀，其中所述自对准硅化物阻挡层防止第一和第二低剂量非MOS晶体管器件阱区域的氧化。

公开(公告)号：US07785983B2

公开(公告)日：2010-08-31

申请号：US11683236

申请日：2007-03-07

申请人： Omar Zia ,  Ruiqi Tian

发明人： Omar Zia ,  Ruiqi Tian

IPC分类号： H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76229 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/8249 ,  H01L21/84

摘要： A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth.

摘要翻译： 一种形成半导体器件的方法包括提供具有第一区域和第二区域的半导体衬底。 第一区域具有一个或多个第一元件，而第二区域具有一个或多个第二元件。 第一个元素与第二个元素不同。 定义了半导体器件上的瓦片特征的瓦片位置和第一瓦片表面区域。 半导体衬底的第一区域和第二区域都形成有源半导体层。 使用负色调掩模在瓷砖位置的有源半导体层中形成第一沟槽。 第一沟槽具有第一深度并且形成瓷砖特征的至少一部分。 使用正色调掩模在有源半导体层中形成第二沟槽。 第二沟槽具有与第一深度不同的第二深度。

公开(公告)号：US20070281446A1

公开(公告)日：2007-12-06

申请号：US11443627

申请日：2006-05-31

申请人： Brian A. Winstead ,  Omar Zia ,  Mariam G. Sadaka ,  Marius K. Orlowski

发明人： Brian A. Winstead ,  Omar Zia ,  Mariam G. Sadaka ,  Marius K. Orlowski

IPC分类号： H01L21/20

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/785

摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first epitaxial semiconductor material from the seed area (98) of the first semiconductor layer (70) that fills the second trench opening (100) and grows laterally over the exposed insulator layer (80) to fill at least part of the first trench opening (99), thereby forming a first epitaxial semiconductor layer (101) that is electrically isolated from the second semiconductor layer (90). By forming a first SOI transistor device (160) over a first SOI layer (90) using deposited (100) silicon and forming first SOI transistor (161) over an epitaxially grown (110) silicon layer (101), a high performance CMOS device is obtained.

摘要翻译： 半导体工艺和装置通过在第一区域（99）中暴露掩埋氧化物层（80）来提供平坦化的混合衬底（18），选择性地蚀刻掩埋氧化物层（80）以暴露第一半导体层 第二较小种子区域（98），然后从填充第二沟槽开口（100）的第一半导体层（70）的种子区域（98）外延生长第一外延半导体材料，并在暴露的绝缘体层上横向生长 80）以填充第一沟槽开口（99）的至少一部分，从而形成与第二半导体层（90）电隔离的第一外延半导体层（101）。 通过使用沉积的（100）硅并在外延生长（110）硅层（101）上形成第一SOI晶体管（161）在第一SOI层（90）上形成第一SOI晶体管器件（160），高性能CMOS器件 获得。

公开(公告)号：US07144784B2

公开(公告)日：2006-12-05

申请号：US10902218

申请日：2004-07-29

申请人： Byoung W. Min ,  Nigel G. Cave ,  Venkat R. Kolagunta ,  Omar Zia ,  Sinan Goktepeli

发明人： Byoung W. Min ,  Nigel G. Cave ,  Venkat R. Kolagunta ,  Omar Zia ,  Sinan Goktepeli

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/518

摘要： In one embodiment, a method for forming a semiconductor device is described. A semiconductor substrate has a first portion and a second portion. A first dielectric layer formed over the first portion of the semiconductor substrate and a second dielectric layer is formed over the second portion of the semiconductor substrate. A cap that may include silicon, such as polysilicon, is formed over the first dielectric layer. A first electrode layer is formed over the cap and a second electrode layer is formed over the second dielectric.

公开(公告)号：US07067342B2

公开(公告)日：2006-06-27

申请号：US10988963

申请日：2004-11-15

申请人： Omar Zia ,  Nigel G. Cave ,  Lawrence Cary Gunn, III

发明人： Omar Zia ,  Nigel G. Cave ,  Lawrence Cary Gunn, III

IPC分类号： H01L21/00 ,  H01L21/336

CPC分类号： H01L27/0617 ,  H01L21/84

摘要： A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately optimized. The transistor has a salicide for source/drain contacts. During this process, a salicide block is used over the waveguide to prevent salicide formation in unwanted areas of the waveguide. The depth of the trench for the waveguide can be lower than that of the trench for the transistor isolation. Trench isolation depth can be set by an etch stop region that can be either a thin oxide layer or a buffer layer that is selectively etchable with respect to the top semiconductor layer and that can be used as a seed layer for growing the top semiconductor layer.

摘要翻译： 半导体结构在同一集成电路上具有波导晶体管。 一种沟槽隔离技术用于限定晶体管区域，另一种用于优化波导的横向边界。 波导和晶体管都具有可以单独优化的具有衬垫的沟槽。 晶体管具有用于源/漏触点的自对准硅。 在该过程中，在波导上使用自对准硅化物块以防止波导的不需要的区域中的自对准硅化物形成。 用于波导的沟槽的深度可以低于用于晶体管隔离的沟槽的深度。 沟槽隔离深度可以通过可以是相对于顶部半导体层可选择性蚀刻的薄氧化物层或缓冲层的蚀刻停止区域来设置，并且可以用作用于生长顶部半导体层的种子层。

公开(公告)号：US07435639B2

公开(公告)日：2008-10-14

申请号：US11443627

申请日：2006-05-31

申请人： Brian A. Winstead ,  Omar Zia ,  Mariam G. Sadaka ,  Marius K. Orlowski

发明人： Brian A. Winstead ,  Omar Zia ,  Mariam G. Sadaka ,  Marius K. Orlowski

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/785

摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first epitaxial semiconductor material from the seed area (98) of the first semiconductor layer (70) that fills the second trench opening (100) and grows laterally over the exposed insulator layer (80) to fill at least part of the first trench opening (99), thereby forming a first epitaxial semiconductor layer (101) that is electrically isolated from the second semiconductor layer (90). By forming a first SOI transistor device (160) over a first SOI layer (90) using deposited (100) silicon and forming first SOI transistor (161) over an epitaxially grown (110) silicon layer (101), a high performance CMOS device is obtained.

摘要翻译： 半导体工艺和装置通过在第一区域（99）中暴露掩埋氧化物层（80）来提供平坦化的混合衬底（18），选择性地蚀刻掩埋氧化物层（80）以暴露第一半导体层 第二较小种子区域（98），然后从填充第二沟槽开口（100）的第一半导体层（70）的种子区域（98）外延生长第一外延半导体材料，并在暴露的绝缘体层上横向生长 80）以填充第一沟槽开口（99）的至少一部分，从而形成与第二半导体层（90）电隔离的第一外延半导体层（101）。 通过使用沉积的（100）硅并在外延生长（110）硅层（101）上形成第一SOI晶体管（161）在第一SOI层（90）上形成第一SOI晶体管器件（160），高性能CMOS器件 获得。