公开(公告)号：US07109051B2

公开(公告)日：2006-09-19

申请号：US10989940

申请日：2004-11-15

Applicant: Nigel G. Cave ,  Omar Zia

Inventor： Nigel G. Cave ,  Omar Zia

IPC: H01L21/00 ,  H01L21/338

CPC classification number: H01L27/144 ,  H01L27/15

Abstract: A method for integrating an optical device and an electronic device on a semiconductor substrate comprises forming openings within an active semiconductor layer in a first region of the semiconductor substrate, wherein the first region corresponds to an electronic device portion and the second region corresponds to an optical device portion. A semiconductor layer is epitaxially grown overlying an exposed active semiconductor layer in the second region, the epitaxially grown semiconductor layer corresponding to an optical device region. At least a portion of an electronic device is formed on the active semiconductor layer within the electronic device portion of the semiconductor substrate. The method further includes forming openings within the epitaxially grown semiconductor layer of the optical device portion of the semiconductor substrate, wherein the openings define one or more features of an optical device.

公开(公告)号：US06924184B2

公开(公告)日：2005-08-02

申请号：US10394352

申请日：2003-03-21

Applicant: Nigel G. Cave ,  Anna M. Phillips ,  Terry G. Sparks

Inventor： Nigel G. Cave ,  Anna M. Phillips ,  Terry G. Sparks

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/48

CPC classification number: H01L21/76819 ,  H01L21/76802 ,  H01L21/76835

Abstract: Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.

Abstract translation: 通孔到晶体管的源极/漏极被制成具有非常均匀的深度，使得光致抗蚀剂厚度可以最小化，以减少与以最小间距的小孔通孔和通孔相关的问题。 这是通过将栅极堆叠上的电介质抛光到存在于栅极堆叠上的抛光停止来实现的，以使得具有与栅极堆叠上的抛光停止层的顶表面共面的顶表面。 这建立了在晶片上方的衬底上高度非常均匀的顶表面。 因此，在该顶表面上形成的随后的电介质在晶片上的高度也是非常均匀的。 基于期望保持用于蚀刻的图案通过非常均匀的厚度的层，光致抗蚀剂厚度然后可以被选择为所需的最小厚度。

公开(公告)号：US07262105B2

公开(公告)日：2007-08-28

申请号：US10718892

申请日：2003-11-21

Applicant: Dharmesh Jawarani ,  Nigel G. Cave ,  Michael Rendon

Inventor： Dharmesh Jawarani ,  Nigel G. Cave ,  Michael Rendon

IPC: H01L21/336 ,  H01L21/425 ,  H01L21/44

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6656

Abstract: In a semiconductor device, a relatively deep germanium implant and activation thereof precedes deposition of the nickel for nickel silicide formation. The activation of the germanium causes the lattice constant in the region of the implant to be increased over the lattice constant of the background substrate, which is preferably silicon. The effect is that the lattice so altered avoids formation of nickel disilicide. The result is that the nickel silicide spiking is avoided.

Abstract translation: 在半导体器件中，相对较深的锗注入和激活之前，镍沉积镍硅化镍形成之前。 锗的激活导致植入物区域中的晶格常数在背景衬底（其优选为硅）的晶格常数上增加。 效果是，如此改变的晶格避免形成二硅化镍。 结果是避免了硅化镍尖峰。

公开(公告)号：US06313024B1

公开(公告)日：2001-11-06

申请号：US09394190

申请日：1999-09-10

Applicant: Nigel G. Cave ,  Kathleen C. Yu ,  Janos Farkas

Inventor： Nigel G. Cave ,  Kathleen C. Yu ,  Janos Farkas

IPC: H01L2144

CPC classification number: H01L24/05 ,  H01L23/5329 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract translation: 在本发明的一个实施例中，导电支撑结构（112）形成在层间电介质层内。 导电支撑结构（112）位于集成电路的接合焊盘区域（111）内，并且对具有低杨氏模量的层间电介质层的部分提供支撑。 导电支撑结构（112）使用用于在集成电路的器件区域（109）中形成金属互连的相同工艺形成，但它们不电耦合到位于器件区域（109）内的半导体器件， 。 导电支撑结构（114）也形成在划线区域（104）内，以提供对集成电路的该区域中的层间电介质层的支撑。

公开(公告)号：US6037668A

公开(公告)日：2000-03-14

申请号：US191353

申请日：1998-11-13

Applicant: Nigel G. Cave ,  Kathleen C. Yu ,  Janos Farkas

Inventor： Nigel G. Cave ,  Kathleen C. Yu ,  Janos Farkas

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/485 ,  H01L23/532 ,  H01L27/04 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L23/5329 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract translation: 在本发明的一个实施例中，导电支撑结构（112）形成在层间电介质层内。 导电支撑结构（112）位于集成电路的接合焊盘区域（111）内，并且对具有低杨氏模量的层间电介质层的部分提供支撑。 导电支撑结构（112）使用用于在集成电路的器件区域（109）中形成金属互连的相同工艺形成，但它们不电耦合到位于器件区域（109）内的半导体器件， 。 导电支撑结构（114）也形成在划线区域（104）内，以提供对集成电路的该区域中的层间电介质层的支撑。

公开(公告)号：US07144784B2

公开(公告)日：2006-12-05

申请号：US10902218

申请日：2004-07-29

Applicant: Byoung W. Min ,  Nigel G. Cave ,  Venkat R. Kolagunta ,  Omar Zia ,  Sinan Goktepeli

Inventor： Byoung W. Min ,  Nigel G. Cave ,  Venkat R. Kolagunta ,  Omar Zia ,  Sinan Goktepeli

IPC: H01L21/336 ,  H01L21/8242 ,  H01L21/3205

CPC classification number: H01L21/823842 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/518

Abstract: In one embodiment, a method for forming a semiconductor device is described. A semiconductor substrate has a first portion and a second portion. A first dielectric layer formed over the first portion of the semiconductor substrate and a second dielectric layer is formed over the second portion of the semiconductor substrate. A cap that may include silicon, such as polysilicon, is formed over the first dielectric layer. A first electrode layer is formed over the cap and a second electrode layer is formed over the second dielectric.

公开(公告)号：US07067342B2

公开(公告)日：2006-06-27

申请号：US10988963

申请日：2004-11-15

Applicant: Omar Zia ,  Nigel G. Cave ,  Lawrence Cary Gunn, III

Inventor： Omar Zia ,  Nigel G. Cave ,  Lawrence Cary Gunn, III

IPC: H01L21/00 ,  H01L21/336

CPC classification number: H01L27/0617 ,  H01L21/84

Abstract: A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately optimized. The transistor has a salicide for source/drain contacts. During this process, a salicide block is used over the waveguide to prevent salicide formation in unwanted areas of the waveguide. The depth of the trench for the waveguide can be lower than that of the trench for the transistor isolation. Trench isolation depth can be set by an etch stop region that can be either a thin oxide layer or a buffer layer that is selectively etchable with respect to the top semiconductor layer and that can be used as a seed layer for growing the top semiconductor layer.

Abstract translation: 半导体结构在同一集成电路上具有波导晶体管。 一种沟槽隔离技术用于限定晶体管区域，另一种用于优化波导的横向边界。 波导和晶体管都具有可以单独优化的具有衬垫的沟槽。 晶体管具有用于源/漏触点的自对准硅。 在该过程中，在波导上使用自对准硅化物块以防止波导的不需要的区域中的自对准硅化物形成。 用于波导的沟槽的深度可以低于用于晶体管隔离的沟槽的深度。 沟槽隔离深度可以通过可以是相对于顶部半导体层可选择性蚀刻的薄氧化物层或缓冲层的蚀刻停止区域来设置，并且可以用作用于生长顶部半导体层的种子层。