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公开(公告)号：US09240783B2
公开(公告)日：2016-01-19
申请号：US14295658
申请日：2014-06-04
申请人： Onkyo Corporation
摘要： A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.
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公开(公告)号：US09787319B2
公开(公告)日：2017-10-10
申请号：US15137129
申请日：2016-04-25
申请人： Onkyo Corporation
CPC分类号： H03M3/37 , G11B20/10009 , G11B2020/00065 , H03M3/30 , H03M3/346 , H03M3/348 , H03M3/424 , H04R3/00
摘要： Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
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公开(公告)号：US09590654B2
公开(公告)日：2017-03-07
申请号：US14594329
申请日：2015-01-12
申请人： Onkyo Corporation
IPC分类号： H03M3/00
摘要： Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
摘要翻译： 提供了可以实时校正输出状态并减少由延迟装置产生的失真/噪声分量的影响的电路。 信号调制电路包括减法器，积分器，相位反相电路，用于在与时钟信号同步的定时插入零电平的DFF，对信号进行延迟和量化;三态信号发生电路，用于选择性地产生三态信号 将连接到单个电源的负载驱动为包括正电流导通状态，负电流导通状态和截止状态的三态导通状态，用于产生用于驱动负载的驱动信号的驱动电路和反馈 用于将驱动信号从驱动电路反馈到输入信号的电路。
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公开(公告)号：US09287867B2
公开(公告)日：2016-03-15
申请号：US14295658
申请日：2014-06-04
申请人： Onkyo Corporation
CPC分类号： H03K19/0002 , H03K19/09443 , H03K19/21 , H03M3/30 , H04L25/4923 , H04L25/4925
摘要： A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.
摘要翻译： 具有通用性的电路合成一位数字信号以产生三进制信号。 脉冲合成电路从两个DFF合成一位数字信号，生成三态信号。 脉冲合成电路具有第一或非门，第二或非门，第三或非门和三个开关。 第一开关连接到第一电位，第二开关连接到第二电位，第三开关连接到第三电位。 根据来自两个DFF的信号的逻辑值，第一至第三开关被接通/断开，并且将第一电位，第二电位和第三电位中的任一个设置为输出电位，使得三元 生成信号。
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公开(公告)号：US09350378B2
公开(公告)日：2016-05-24
申请号：US14295587
申请日：2014-06-04
申请人： Onkyo Corporation
CPC分类号： H03M3/37 , G11B20/10009 , G11B2020/00065 , H03M3/30 , H03M3/346 , H03M3/348 , H03M3/424 , H04R3/00
摘要： Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtracter, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
摘要翻译： 提供了可以实时校正输出状态并可靠地调制输入信号以输出调制信号的调制电路。 信号调制电路包括减法器，积分器，斩波电路，分频器和D型触发器。 Σ-Δ调制电路的延迟电路不提供给反馈电路，并且在D型触发器中延迟和量化信号。 斩波电路在与时钟信号同步的定时插入零电平，从而执行脉冲密度调制。
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公开(公告)号：US08970269B2
公开(公告)日：2015-03-03
申请号：US14132595
申请日：2013-12-18
申请人： Onkyo Corporation
发明人： Yoshinori Nakanishi , Mamoru Sekiya
摘要： A pulse width modulation signal with a less distortion component that is not influenced by a common-mode noise or an offset voltage is generated. Pulse signal generation circuits 6, 7 generate pulse signals S1, S2 whose pulse widths are discharge times t1, t2 of integrators 3, 4, respectively, a PWM signal generation circuit 8 detects discharge end timings of the integrators 3, 4 based on the pulse signals S1, S2, and a pulse whose pulse width is a time between discharge end timing of one of the integrators 4 and discharge end timing of the other one of the integrators 3 is generated so as to be output as a PWM signal Spwm.
摘要翻译： 产生不受共模噪声或偏移电压影响的具有较小失真分量的脉宽调制信号。 脉冲信号产生电路6,7产生脉冲宽度分别为脉冲宽度为积分器3,4的放电时间t1，t2的脉冲信号S1，S2，PWM信号产生电路8根据脉冲信号产生电路8检测积分器3,4的放电结束定时 产生信号S1，S2，并且产生脉冲宽度为积分器4之一的放电结束定时与另一个积分器3的放电结束定时之间的时间的脉冲，以便作为PWM信号Spwm输出。
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