公开(公告)号：US20170017492A1

公开(公告)日：2017-01-19

申请号：US15282082

申请日：2016-09-30

申请人： Oren Ben-Kiki ,  ILAN PARDO ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

发明人： Oren Ben-Kiki ,  ILAN PARDO ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

IPC分类号： G06F9/38 ,  G06F12/0875 ,  G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3881 ,  G06F9/54 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0772 ,  G06F12/0875 ,  G06F2212/452

摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.

公开(公告)号：US20170017491A1

公开(公告)日：2017-01-19

申请号：US15281944

申请日：2016-09-30

申请人： Oren Ben-Kiki ,  ILAN PARDO ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

发明人： Oren Ben-Kiki ,  ILAN PARDO ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

IPC分类号： G06F9/38 ,  G06F12/0875 ,  G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3881 ,  G06F9/54 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0772 ,  G06F12/0875 ,  G06F2212/452

摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.

摘要翻译： 描述了一种用于提供加速器的低延迟调用的装置和方法。 例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括用于调用一个或多个加速器命令的加速器调用指令的多个指令，所述加速器调用指令将指定所述命令的命令数据存储在所述命令寄存器内; 一个或多个加速器，用于从命令寄存器读取命令数据，并且响应地尝试执行由命令数据识别的命令，其中如果一个或多个加速器成功执行命令，则一个或多个加速器将存储包括 结果寄存器中的命令结果; 并且如果一个或多个加速器不能成功地执行命令，则一个或多个加速器将存储指示不能执行该命令的原因的结果数据，其中执行逻辑将暂停执行，直到加速器完成执行或被中断 其中所述加速器包括用于存储其状态的逻辑，如果被中断，使得其可以在稍后的时间继续执行。

公开(公告)号：US20140189332A1

公开(公告)日：2014-07-03

申请号：US13729915

申请日：2012-12-28

申请人： Oren Ben-Kiki ,  Ilan Pardo ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

发明人： Oren Ben-Kiki ,  Ilan Pardo ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3881 ,  G06F9/54 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0772 ,  G06F12/0875 ,  G06F2212/452

摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the command could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands; and one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data.

摘要翻译： 描述了一种用于提供加速器的低延迟调用的装置和方法。 例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或表示无法执行命令的原因的数据; 执行逻辑以执行包括调用一个或多个加速器命令的加速器调用指令的多个指令; 以及一个或多个加速器，用于从命令寄存器读取命令数据，并且响应地尝试执行由命令数据识别的命令。

公开(公告)号：US09053025B2

公开(公告)日：2015-06-09

申请号：US13729931

申请日：2012-12-28

申请人： Oren Ben-Kiki ,  Ilan Pardo ,  Robert Valentine

发明人： Oren Ben-Kiki ,  Ilan Pardo ,  Robert Valentine

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F9/38

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1438

摘要： A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the instruction failure logic to be used for instructions which have complex failure modes and which are expected to have a failure frequency above a threshold, wherein the operations include: detecting an instruction execution failure and determining a reason for the failure; storing failure data in a destination register to indicate the failure and to specify details associated with the failure; and allowing application program code to read the failure data and responsively take one or more actions responsive to the failure, wherein the instruction failure logic performs its operations without invocation of an exception handler or switching to a low level domain on a system which employs hierarchical protection domains.

摘要翻译： 描述了一种处理器，包括：响应于检测到的指令执行失败执行多个操作的指令失败逻辑，用于具有复杂故障模式并且预期具有高于阈值的故障频率的指令的指令故障逻辑 其中，所述操作包括：检测指令执行失败并确定所述故障的原因; 将故障数据存储在目的地寄存器中以指示故障并指定与故障相关的细节; 并且允许应用程序代码读取故障数据并且响应于故障响应地采取一个或多个动作，其中指令失败逻辑执行其操作而不调用异常处理程序或切换到采用分级保护的系统上的低级域 域名

公开(公告)号：US20140189426A1

公开(公告)日：2014-07-03

申请号：US13729931

申请日：2012-12-28

申请人： Oren Ben-Kiki ,  Ilan Pardo ,  Robert Valentine

发明人： Oren Ben-Kiki ,  Ilan Pardo ,  Robert Valentine

IPC分类号： G06F11/07

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1438

摘要： A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the instruction failure logic to be used for instructions which have complex failure modes and which are expected to have a failure frequency above a threshold, wherein the operations include: detecting an instruction execution failure and determining a reason for the failure; storing failure data in a destination register to indicate the failure and to specify details associated with the failure; and allowing application program code to read the failure data and responsively take one or more actions responsive to the failure, wherein the instruction failure logic performs its operations without invocation of an exception handler or switching to a low level domain on a system which employs hierarchical protection domains.

摘要翻译： 描述了一种处理器，包括：响应于检测到的指令执行失败执行多个操作的指令失败逻辑，用于具有复杂故障模式并且预期具有高于阈值的故障频率的指令的指令故障逻辑 其中，所述操作包括：检测指令执行失败并确定所述故障的原因; 将故障数据存储在目的地寄存器中以指示故障并指定与故障相关的细节; 并且允许应用程序代码读取故障数据并且响应于故障响应地采取一个或多个动作，其中指令失败逻辑执行其操作而不调用异常处理程序或切换到采用分级保护的系统上的低级域 域名

公开(公告)号：US20140189191A1

公开(公告)日：2014-07-03

申请号：US13730030

申请日：2012-12-28

申请人： Ilan Pardo ,  Michael Behar ,  Oren Ben-Kiki ,  Dror Markovich

发明人： Ilan Pardo ,  Michael Behar ,  Oren Ben-Kiki ,  Dror Markovich

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F12/0875 ,  G06F12/0897 ,  Y02D10/13

摘要： A processor is described comprising: an architectural register file implemented as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, and a data location table (DLT) to store data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache.

摘要翻译： 描述了一种处理器，包括：实现为级别1（L1）数据高速缓存中的寄存器文件高速缓存和架构寄存器区域的组合的架构寄存器文件，以及数据位置表（DLT），用于存储指示每个 寄存器文件缓存内的架构寄存器和/或L1数据高速缓存内的体系结构寄存器区域。

公开(公告)号：US20160283237A1

公开(公告)日：2016-09-29

申请号：US14671914

申请日：2015-03-27

申请人： Ilan Pardo ,  Oren Ben-Kiki ,  Arch D. Robison ,  Nadav Chachmon ,  James H. Cownie

发明人： Ilan Pardo ,  Oren Ben-Kiki ,  Arch D. Robison ,  Nadav Chachmon ,  James H. Cownie

IPC分类号： G06F9/30 ,  G06F9/355

CPC分类号： G06F9/3001 ,  G06F9/30018 ,  G06F9/3004 ,  G06F9/526

摘要： Instructions and logic provide atomic range operations in a multiprocessing system. In one embodiment an atomic range modification instruction specifies an address for a set of range indices. The instruction locks access to the set of range indices and loads the range indices to check the range size. The range size is compared with a size sufficient to perform the range modification. If the range size is sufficient to perform the range modification, the range modification is performed and one or more modified range indices of the set of range indices is stored back to memory. Otherwise an error signal is set when the range size is not sufficient to perform said range modification. Access to the set of range indices is unlocked responsive to completion of the atomic range modification instruction. Embodiments may include atomic increment next instructions, add next instructions, decrement end instructions, and/or subtract end instructions.

摘要翻译： 说明和逻辑在多处理系统中提供原子范围操作。 在一个实施例中，原子范围修改指令指定一组范围索引的地址。 该指令锁定对范围索引的访问，并加载范围索引以检查范围大小。 将范围大小与足以执行范围修改的大小进行比较。 如果范围大小足以进行范围修改，则执行范围修改，并且将范围索引集合中的一个或多个修改的范围索引存储回存储器。 否则当范围大小不足以执行所述范围修改时，设置错误信号。 响应于原子范围修改指令的完成，对范围索引集的访问被解锁。 实施例可以包括原子增量下一个指令，添加下一个指令，递减结束指令和/或减去结束指令。

公开(公告)号：US20140189333A1

公开(公告)日：2014-07-03

申请号：US13730143

申请日：2012-12-28

申请人： Oren Ben-Kiki ,  Ilan Pardo ,  Eliezer Weissmann

发明人： Oren Ben-Kiki ,  Ilan Pardo ,  Eliezer Weissmann

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/30054 ,  G06F9/30189 ,  G06F9/3881

摘要： A processor comprising: execution logic to execute a first thread including an accelerator invocation instruction to invoke an accelerator command; an accelerator to execute an accelerator thread in response to the accelerator command, the accelerator to store state data associated with the accelerator thread in a application memory area in memory, wherein prior to executing the accelerator thread, the accelerator is to lock entries in a translation lookaside buffer (TLB) associated with the accelerator thread to prevent an exception which might otherwise result.

摘要翻译： 一种处理器，包括执行逻辑，以执行包括调用加速器命令的加速器调用指令的第一线程; 加速器，其响应于加速器命令执行加速器线程，加速器，用于将与加速器线程相关联的状态数据存储在存储器中的应用存储器区域中，其中在执行加速器线程之前，加速器将锁定条目转换为 与加速器线程相关联的后备缓冲器（TLB），以防止否则可能导致的异常。

公开(公告)号：US20140189317A1

公开(公告)日：2014-07-03

申请号：US13730055

申请日：2012-12-28

申请人： Oren Ben-Kiki ,  Yuval Yosef ,  Ilan Pardo ,  Dror Markovich

发明人： Oren Ben-Kiki ,  Yuval Yosef ,  Ilan Pardo ,  Dror Markovich

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30079 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/46 ,  G06F15/7867 ,  G06F15/7892 ,  G06F15/80

摘要： An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.

摘要翻译： 描述了用于在处理设备上执行延迟优化的执行逻辑和吞吐量优化的执行逻辑的装置和方法。 例如，根据一个实施例的处理器包括：执行第一类型的程序代码的等待时间优化的执行逻辑; 吞吐量优化执行逻辑以执行第二类型的程序代码，其中所述第一类型的程序代码和所述第二类型的程序代码被设计用于相同的指令集架构; 识别过程中的第一类型的程序代码和第二类型的程序代码的逻辑，并且将用于执行的第一类型的程序代码分配在延迟优化的执行逻辑和第二类型的程序代码上以便在吞吐量 - 优化的执行逻辑。

公开(公告)号：US20160246597A1

公开(公告)日：2016-08-25

申请号：US15145748

申请日：2016-05-03

申请人： Oren Ben-Kiki ,  llan Pardo ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

发明人： Oren Ben-Kiki ,  llan Pardo ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3881 ,  G06F9/54 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0772 ,  G06F12/0875 ,  G06F2212/452

摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.

摘要翻译： 描述了一种用于提供加速器的低延迟调用的装置和方法。 例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括用于调用一个或多个加速器命令的加速器调用指令的多个指令，所述加速器调用指令将指定所述命令的命令数据存储在所述命令寄存器内; 一个或多个加速器，用于从命令寄存器读取命令数据并响应于尝试执行由命令数据识别的命令，其中如果一个或多个加速器成功地执行命令，则一个或多个加速器将存储包括 结果寄存器中的命令结果; 并且如果一个或多个加速器不能成功地执行命令，则一个或多个加速器将存储指示不能执行该命令的原因的结果数据，其中执行逻辑将暂停执行，直到加速器完成执行或被中断 其中所述加速器包括用于存储其状态的逻辑，如果被中断，使得其可以在稍后的时间继续执行。