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    Method and system for forward error correction decoding based on a revised error channel estimate
    1.
    发明授权
    Method and system for forward error correction decoding based on a revised error channel estimate 有权
    基于修正误差信道估计的前向纠错解码方法和系统

    公开(公告)号：US09564921B1

    公开(公告)日：2017-02-07

    申请号：US14613805

    申请日：2015-02-04

    申请人： PMC-SIERRA US, INC.

    发明人： Peter Graumann ,  Sean Gibb

    IPC分类号： H03M13/11

    CPC分类号： H03M13/1125 ,  H03M13/1111 ,  H03M13/1131 ,  H03M13/114 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/612 ,  H03M13/6325

    摘要： An FEC codeword comprises channel information indicating the reliability of the information contained by the FEC codeword. The channel information can be used to generate an initial error channel estimate. Based on the initial error channel estimate, an FEC decoder can decode the FEC codeword to increase the reliability of the information contained by the FEC codeword. According to the present disclosure, a method and system of decoding comprises: comparing a current codeword to a previous codeword in order to identify bits corrected between the previous and current codewords; revising an error channel estimate based on the identified corrected bits, the revised estimate representing a change in the error channel over time; and decoding the codeword based on the revised error channel estimate.

    摘要翻译： FEC码字包括指示由FEC码字包含的信息的可靠性的信道信息。 信道信息可用于产生初始误差信道估计。 基于初始误差信道估计，FEC解码器可以对FEC码字进行解码，以增加FEC码字所包含的信息的可靠性。 根据本公开，解码方法和系统包括：将当前码字与先前码字进行比较，以便识别在先前和当前码字之间校正的比特; 基于所识别的校正比特来修正误差信道估计，修正的估计表示误差信道随时间的变化; 以及基于经修改的误差信道估计对码字进行解码。

    Forward error correction decoder system
    3.
    发明授权
    Forward error correction decoder system 有权
    前向纠错解码系统

    公开(公告)号：US09473175B1

    公开(公告)日：2016-10-18

    申请号：US14618583

    申请日：2015-02-10

    申请人： PMC-SIERRA US, INC.

    发明人： Peter Graumann ,  Sean G. Gibb ,  Jonathan Eskritt

    IPC分类号： H03M13/00 ,  H03M13/11

    CPC分类号： H03M13/1111 ,  H03M13/114 ,  H03M13/6505 ,  H03M13/6577 ,  H03M13/6591

    摘要： Forward error correction (FEC) decoders, such as Low Density Parity Check (LDPC) decoders are described. Described FEC decoders minimize the number of internal bits in a layered processor of an LDPC decoder while maintaining high coding gain operation of the LDPC decoder. Minimizing the number of internal bits in a layered processor is achieved by non-linearly companding the soft information into lower precision format while maintaining the dynamic range of the data bits. Described FEC decoders may generate updated soft information having a precision that is equal to the channel precision.

    摘要翻译： 描述了诸如低密度奇偶校验（LDPC）解码器的前向纠错（FEC）解码器。 所描述的FEC解码器在保持LDPC解码器的高编码增益操作的同时，最小化LDPC解码器的分层处理器中的内部比特数。 通过在保持数据位的动态范围的同时将软信息非线性压缩为较低精度格式来实现分层处理器中的内部位数的最小化。 描述的FEC解码器可以生成具有等于信道精度的精度的更新的软信息。

    Reed-solomon decoder
    4.
    发明授权
    Reed-solomon decoder 有权
    里德独奏解码器

    公开(公告)号：US09166623B1

    公开(公告)日：2015-10-20

    申请号：US13803919

    申请日：2013-03-14

    申请人： PMC-SIERRA US, INC.

    发明人： Stephen Bates ,  Peter Graumann ,  Phil Northcott

    IPC分类号： H03M13/00 ,  H03M13/05 ,  H03M13/15

    CPC分类号： H03M13/1515 ,  H03M13/153 ,  H03M13/154 ,  H03M13/1555 ,  H03M13/373 ,  H03M13/45

    摘要： A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The Reed-Solomon decoder also provides hardware area and power savings over more complex Reed-Solomon decoders.

    摘要翻译： 一种使用Reed-Solomon解码器对Reed-Solomon码进行解码的系统和方法，该解码器包括共享单个纠错单元的擦除位置选择器，多个校正子形成器和多个Berlekamp-Massey解码器，以及用于选择Berlekamp-Massey解码器输出 作为错误校正单元的输入。 与已知的硬判决和软判决里德 - 所罗门解码器相比，该方法提高了里德 - 所罗门解码器的误码率性能。 Reed-Solomon解码器还通过更复杂的Reed-Solomon解码器提供硬件面积和功耗。

    High speed gain and phase recovery in presence of phase noise
    5.
    发明授权
    High speed gain and phase recovery in presence of phase noise 有权
    存在相位噪声时的高速增益和相位恢复

    公开(公告)号：US08938037B1

    公开(公告)日：2015-01-20

    申请号：US13798970

    申请日：2013-03-13

    申请人： PMC-Sierra US, Inc.

    发明人： Saeed Fard ,  Sean Gibb ,  Peter Graumann ,  Siavash Sheikh Zeinoddin

    IPC分类号： H04L27/08 ,  H04L1/00

    CPC分类号： H04L1/0036 ,  H04L25/03057 ,  H04L27/2272 ,  H04L27/2657 ,  H04L27/3809

    摘要： A circuit for reducing phase errors in a digital communication systems signal is provided. The circuit comprises a demodulator block, a feed-forward path, a feed-back path, and a slicer. The demodulator block generates a plurality of samples from the signal and determines for each sample a corresponding phase error. The feed-forward path is configured to reduce in the signal a high frequency component of the phase errors. The feed-back path configured to reduce in the signal a low frequency component of the phase errors. The slicer selectively forwards phase errors to the feed-forward path or the feed-back path based on a respective magnitude of the phase error when operating in a decision-directed mode.

    摘要翻译： 提供了用于减少数字通信系统信号中的相位误差的电路。 电路包括解调器块，前馈路径，反馈路径和限幅器。 解调器块从信号中产生多个采样，并为每个采样确定相应的相位误差。 前馈路径被配置为在信号中减少相位误差的高频分量。 反馈路径被配置为在信号中减少相位误差的低频分量。 当在决策模式下操作时，限幅器基于相位误差的相应大小，有选择地将相位误差转发到前馈路径或反馈路径。

    Error correction code decoder with stochastic floor mitigation
    7.
    发明授权
    Error correction code decoder with stochastic floor mitigation 有权
    纠错码解码器随机地板缓解

    公开(公告)号：US09564922B1

    公开(公告)日：2017-02-07

    申请号：US14642072

    申请日：2015-03-09

    申请人： PMC-SIERRA US, INC.

    发明人： Peter Graumann ,  Sean Gibb

    IPC分类号： H03M13/03 ,  H03M13/11

    CPC分类号： H03M13/1142 ,  H03M13/112 ,  H03M13/114 ,  H03M13/3723 ,  H03M13/658

    摘要： A method and apparatus as described herein provide a novel modification to any iterative FEC decoder method that can improve FER performance in the error floor region. Many iterative FEC methods, such as commonly used LDPC decoders, have error floors where the performance of the decoder does not improve below a certain threshold. Error Floors are caused by trapping sets from which traditional methods cannot escape. With Stochastic Floor Mitigation, according to embodiments of the present disclosure, noise is strategically added to the operations occurring during decoding resulting in significantly improved error floor performance.

    摘要翻译： 本文所述的方法和装置提供了可以改善错误楼层区域中的FER性能的任何迭代FEC解码器方法的新颖的修改。 诸如通常使用的LDPC解码器的许多迭代FEC方法具有错误层，其中解码器的性能不会降低到低于某个阈值。 错误楼层是由传统方法无法逃脱的陷阱集引起的。 随着随机楼层减轻，根据本公开的实施例，噪声被策略地添加到在解码期间发生的操作，导致显着改善的错误楼层性能。

    Method and system for decoding encoded data stored in a non-volatile memory
    9.
    发明授权
    Method and system for decoding encoded data stored in a non-volatile memory 有权
    用于解码存储在非易失性存储器中的编码数据的方法和系统

    公开(公告)号：US09170876B1

    公开(公告)日：2015-10-27

    申请号：US14144857

    申请日：2013-12-31

    申请人： PMC-Sierra US, Inc.

    发明人： Stephen Bates ,  Peter Graumann ,  Philip Lyon Northcott ,  Sean Gregory Gibb

    IPC分类号： H03M13/00 ,  G06F11/10

    CPC分类号： G06F11/1048

    摘要： A method of decoding a primary codeword and a set of secondary codewords stored in a non-volatile memory (NVM), which includes reading, from the NVM, the primary codeword and all the secondary codewords and storing them in a second memory. The primary codeword is then read from the second memory and decoded, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector. When the decoding of the primary codeword is unsuccessful: each secondary codeword of the set of secondary codewords is read from the second memory and decoded, utilizing a hard-decision decoder, to identify and correct errored data bits in the each secondary codeword and to determine a location of each errored data bit in the primary codeword. An adjusted LLR vector is generated by adjusting the LLR for each primary codeword data bit based on the determined locations of the errored data bits in the primary codeword.

    摘要翻译： 解码存储在非易失性存储器（NVM）中的主码字和一组次码字的方法，其包括从NVM读取主码字和所有次码字，并将它们存储在第二存储器中。 然后，基于对数似然比（LLR）向量，利用软判决解码器从第二存储器读取主码字并进行解码。 当主代码字的解码不成功时：从第二存储器中读取第二码字集合中的每个辅助码字，并利用硬判决解码器解码以识别和校正每个次码字中的错误数据位并确定 主码字中每个错误数据位的位置。 通过基于所确定的主码字中的错误数据位的位置来调整每个主码字数据位的LLR来生成经调整的LLR向量。