公开(公告)号：US09560039B2

公开(公告)日：2017-01-31

申请号：US14090880

申请日：2013-11-26

申请人： PMC-Sierra US, Inc.

发明人： Dean Kalman ,  Ken Sandars ,  Brett Dolecheck ,  Mike Reyero

IPC分类号： H04L29/00 ,  H04L29/06 ,  G06F21/80 ,  H04L29/08

CPC分类号： H04L63/083 ,  G06F21/805 ,  H04L67/1097

摘要： A method for accessing data in a storage area network is provided. The method initiates with receiving a request for a list of targets on the storage area network. All the targets on the storage area network are exposed to the requestor and authentication requiring a password is requested from the requestor to grant access to the targets on the storage are network. Access to the targets is granted if the password is acceptable, and access to the targets is refused if the password is unacceptable.

摘要翻译： 提供了一种用于访问存储区域网络中的数据的方法。 该方法通过在存储区域网络上接收对目标列表的请求来启动。 存储区域网络上的所有目标都暴露给请求者，并且请求来自请求者的认证需要授权访问存储网络上的目标。 如果密码是可接受的，则授予目标访问权限，如果密码不可接受，则拒绝对目标的访问。

公开(公告)号：US09529963B1

公开(公告)日：2016-12-27

申请号：US14859158

申请日：2015-09-18

申请人： PMC-SIERRA US, INC.

发明人： Theodore Andrew Wilson

IPC分类号： G06F17/50 ,  G01R31/28

CPC分类号： G01R31/2851 ,  G01R31/31835 ,  G01R31/318357

摘要： A method of partitioning a verification test bench, the method comprising: receiving a source code of the verification test bench, the source code comprising reactive components for sending test traffic to a design under test (DUT) and for receiving test traffic from the DUT, the source code further comprising analytic components for verifying the test traffic between the reactive components and the DUT; identifying the analytic components in the source code; compiling the reactive components and the DUT into a first executable test bench that can be run in a regression to generate test traffic between the reactive components and the DUT; and compiling the analytic components into a second executable test bench that can be run separately from the first executable test bench in order to verify the test traffic.

摘要翻译： 一种对验证测试台进行分区的方法，所述方法包括：接收验证测试台的源代码，所述源代码包括用于将测试业务发送到被测设计（DUT）的反应组件，以及用于从DUT接收测试业务， 所述源代码还包括用于验证所述无功部件和所述DUT之间的所述测试业务的分析部件; 识别源代码中的分析组件; 将无功组件和DUT编译成可在回归中运行以在无功组件和DUT之间产生测试业务的第一可执行测试台; 并将分析组件编译成可以与第一个可执行测试台分开运行的第二个可执行测试台，以验证测试流量。

公开(公告)号：US09431956B1

公开(公告)日：2016-08-30

申请号：US14814201

申请日：2015-07-30

申请人： PMC-SIERRA US, INC.

发明人： Hormoz Djahanshahi ,  Su-Tarn Lim

IPC分类号： H03B5/06 ,  H03B5/36 ,  H03L3/00

CPC分类号： H03B5/326 ,  H03B5/06 ,  H03B5/30 ,  H03B5/36 ,  H03B5/364 ,  H03B2200/0034 ,  H03B2200/0046 ,  H03B2200/009 ,  H03B2200/0094 ,  H03L3/00

摘要： An oscillator and method for generating a signal are provided. The oscillator comprises an electro-mechanical resonator and a reconfigurable oscillator driver. The reconfigurable oscillator driver starts the oscillator in single-ended mode to avoid latching and transitions the oscillator to differential mode in such a manner as to sustain oscillations therein. The reconfigurable oscillator driver comprises two back-to-back banks of inverters and an adjustable feedback resistor. In single-ended mode, one bank is disabled and the other bank is enabled. To transition to differential mode and improve the quality of the signal, the number of enabled inverters is equalized in both banks.

公开(公告)号：US09336173B1

公开(公告)日：2016-05-10

申请号：US14136476

申请日：2013-12-20

申请人： PMC-Sierra US, Inc.

发明人： Richard David Sodke ,  Kuan Hua Tan ,  Robert Kristian Watson ,  Larrie Simon Carr

IPC分类号： G06F13/40

CPC分类号： G06F13/4022 ,  G06F3/0619 ,  G06F3/0665 ,  G06F3/0689 ,  G06F13/4027 ,  G06F13/4282

摘要： The disclosure generally relates to a PCIe switch that includes a selectively transparent bridge that selectively allows transactions to traverse between multiple PCIe domains without the encumbrance of each root complex entity requiring knowledge of the selectively transparent bridge. The bridge that enables the transactions is invisible to the root complex entity in a host and drive switch domain of the PCIe switch. No address translation of the transactions is required because the drive switch domain address map is a subset of the host switch domain address map. The bridge allows for extremely low latency transactions between host systems and storage drives because the bridge allows the storage drive to read the Direct Memory Access (DMA) Scatter-Gather List (SGL) directly from host memory. The bridge also allows I/O data reads and writes from the storage drive directly to the host memory without store and forward within a RAID controller's memory.

摘要翻译： 本公开通常涉及PCIe交换机，其包括选择性地透明的桥，其选择性地允许事务在多个PCIe域之间穿越，而不需要知道选择性透明桥的每个根复杂实体的阻碍。 启用交易的网桥对于PCIe交换机的主机和驱动器交换机域中的根复合实体是不可见的。 由于驱动交换机域地址映射是主机交换机域地址映射的子集，所以不需要交易的地址转换。 桥接器允许在主机系统和存储驱动器之间进行极低延迟的交易，因为该桥接器允许存储驱动器直接从主机存储器读取直接存储器访问（DMA）分散收集列表（SGL）。 桥接器还允许从存储驱动器将I / O数据读取和写入直接存储到主机存储器，而无需在RAID控制器的存储器内存储和转发。

公开(公告)号：US09280508B1

公开(公告)日：2016-03-08

申请号：US14042132

申请日：2013-09-30

申请人： PMC-Sierra US, Inc.

发明人： Gregory Arthur Tabor ,  Larrie Simon Carr ,  Richard David Sodke

IPC分类号： G06F13/20 ,  G06F13/14 ,  G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4022

摘要： Provided is an apparatus and method for enabling interoperability between a serial attached small computer system interface (SAS) protocol with a peripheral component interconnect express (PCIe) protocol. A SAS-PCIe bridge includes a SAS component configured to communicate with a SAS device in a SAS domain and a PCIe component configured to communicate with a PCIe switch in a PCIe domain. The SAS component and the PCIe component are configured to convert data between the SAS protocol and the PCIe protocol.

摘要翻译： 提供了一种用于实现串行连接的小型计算机系统接口（SAS）协议与外围组件互连快速（PCIe）协议之间的互操作性的装置和方法。 SAS-PCIe桥接器包括配置为与SAS域中的SAS设备进行通信的SAS组件和配置为与PCIe域中的PCIe交换机通信的PCIe组件。 SAS组件和PCIe组件配置为在SAS协议和PCIe协议之间转换数据。

公开(公告)号：US09276874B1

公开(公告)日：2016-03-01

申请号：US13839961

申请日：2013-03-15

申请人： PMC-Sierra US, Inc.

发明人： Winston Ki-Cheong Mok ,  Jayeshkumar Roonwal ,  Kishor Ashanand Ruparel

IPC分类号： H04J3/16 ,  H04L12/931 ,  H04L12/861 ,  H04L12/939

CPC分类号： H04L49/552 ,  H04J3/16 ,  H04J3/1617 ,  H04L7/042 ,  H04L49/90

摘要： A system and method of delineating GFP data. The GFP framer comprises a candidate generator for generating an array of core header candidates from a data word received on a data bus, a candidate processor for generating a plurality of candidate tours and a frame delineator for identifying a candidate tour as an active tour and delineating the boundaries of the GFP frames defined by the active tour. Each core header candidate defines a reference position of one of the plurality of candidate tours. Each of the plurality of candidate tour comprises a record of core header positions for a series of GFP frames from the data word.

摘要翻译： 描述GFP数据的系统和方法。 GFP成帧器包括候选发生器，用于从数据总线上接收的数据字生成核心标题候选的阵列，用于产生多个候选旅行的候选处理器和用于识别作为活动巡视的候选游览的帧描绘符，并且描绘 由主动巡视定义的GFP帧的边界。 每个核心头候选者定义多个候选旅游之一的参考位置。 多个候选巡视中的每一个包括来自数据字的一系列GFP帧的核心头部位置的记录。

公开(公告)号：US09257144B1

公开(公告)日：2016-02-09

申请号：US14688696

申请日：2015-04-16

申请人： PMC-SIERRA US, INC.

发明人： Dong Zhang

IPC分类号： G11B5/596 ,  G11B20/12

CPC分类号： G11B20/1217 ,  G11B2020/1238

摘要： A system for writing data to overlapping physical tracks of a shingled magnetic record (SMR) hard disk drive (HDD) and a method for creating a logical disk from overlapping physical tracks of the SMR HDD. The system comprises a write header and a memory identifying the overlapping physical tracks which are accessible through the logical disk. The physical tracks are spaced from each other by at least the width of the write header. The method comprises mapping in a memory the logical disk to writeable tracks of the overlapping physical tracks, the writeable tracks spaced from each other by at least the width of the write header.

摘要翻译： 一种用于将数据写入带有杂音磁记录（SMR）硬盘驱动器（HDD）的重叠物理轨道的系统以及用于从SMR HDD的重叠物理轨道创建逻辑磁盘的方法。 该系统包括写入头部和识别通过逻辑盘可访问的重叠物理轨道的存储器。 物理磁道彼此至少间隔开写头的宽度。 该方法包括将存储器中的逻辑盘映射到重叠物理轨道的可写轨道，该可写轨迹彼此间隔至少写入报头的宽度。

公开(公告)号：US20160004458A1

公开(公告)日：2016-01-07

申请号：US14325212

申请日：2014-07-07

申请人： PMC-SIERRA US, INC.

发明人： Rino Micheloni ,  Alessia Marelli ,  Luca Crippa

IPC分类号： G06F3/06

CPC分类号： G06F3/0616 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00

摘要： A system and method for memory block pool wear leveling in a nonvolatile memory device. An improved bit error rate for the nonvolatile memory system is attained by identifying a plurality of memory block pools of the nonvolatile memory system, identifying a relaxation time delay for each of the plurality of memory block pools and executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of the memory block pools.

摘要翻译： 用于非易失性存储器件中的存储块池擦除均衡的系统和方法。 通过识别非易失性存储器系统的多个存储器块池来识别非易失性存储器系统的改进的误码率，识别多个存储器块池中的每一个的松弛时间延迟并执行预定数量的编程/擦除周期 基于所述存储器块池的所述弛豫时间延迟，针对所述多个存储器块池中的每一个。

公开(公告)号：US09231600B1

公开(公告)日：2016-01-05

申请号：US14791321

申请日：2015-07-03

申请人： PMC-SIERRA US, INC.

发明人： Hormoz Djahanshahi ,  William Michael Lye

IPC分类号： H03L7/18 ,  H03L7/093 ,  H03L7/07 ,  H03L7/087 ,  H03L7/099 ,  H03L7/197

CPC分类号： H03L7/07 ,  H03L7/087 ,  H03L7/099 ,  H03L7/185 ,  H03L7/1974 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03L2207/12 ,  H04L7/0025 ,  H04L7/0331 ,  H04L7/0332

摘要： A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

公开(公告)号：US09219470B1

公开(公告)日：2015-12-22

申请号：US13873817

申请日：2013-04-30

申请人： PMC-SIERRA US, INC.

发明人： Michael Ben Venditti

IPC分类号： G06F1/04 ,  G06F11/00 ,  H03K3/017

CPC分类号： H03K5/1565

摘要： A circuit and method for improving signal integrity characteristics of a non-full rate transmitter are disclosed herein. The circuit comprises an actuator block having an input for receiving a differential clock signal, the differential clock signal comprising a positive clock signal and a negative clock signal, the actuator configured to adjust a difference between the positive and negative clock signals; a sensing block, for sensing a difference between positive and negative signals of a differential signal, the differential signal being related to the clock signal; and a calibration block for providing a control signal to the actuator based on the sensed difference between the positive and negative signals.

摘要翻译： 本文公开了一种用于改善非全速率发射器的信号完整性特性的电路和方法。 所述电路包括具有用于接收差分时钟信号的输入的致动器块，所述差分时钟信号包括正时钟信号和负时钟信号，所述致动器被配置为调整所述正时钟信号和所述正时钟信号之间的差; 感测块，用于感测差分信号的正和负信号之间的差异，差分信号与时钟信号有关; 以及校准块，用于基于感测到的正和负信号的差异向致动器提供控制信号。