公开(公告)号：US07312654B2

公开(公告)日：2007-12-25

申请号：US11314203

申请日：2005-12-20

申请人： William J. Roeckner ,  Pallab Midya ,  Patrick L. Rakers ,  Lawrence E. Connell ,  Daniel A. Mavencamp ,  Bradley C. Stewart

发明人： William J. Roeckner ,  Pallab Midya ,  Patrick L. Rakers ,  Lawrence E. Connell ,  Daniel A. Mavencamp ,  Bradley C. Stewart

IPC分类号： H03F3/38

CPC分类号： H03F3/2173 ,  H03F1/305 ,  H03F3/2171 ,  H03F3/72 ,  H03F2200/03 ,  H03F2200/351 ,  H03K17/161

摘要： A closed loop audio amplifier system and method of powering up/down the system without producing audible artifacts are provided. During power up, a prebias voltage is provided to each output connected to a speaker to increase the voltage to a nominal output level. High impedance switches are then driven at a 50% duty cycle. Feedback from the output is supplied to a servo, which is enabled to fine tune the output voltage. Low impedance switches are then driven at a 50% duty cycle at a quarter cycle timing. The order of the feedback loop depends on which of the high or low impedance switches are driven. The prebias voltage is then removed before audio signals to be amplified are supplied to the system. Timing of driving of the switches is programmable. To power down, essentially the reverse sequence is provided.

摘要翻译： 提供一种闭环音频放大器系统以及在不产生可听见的伪影的情况下对系统加电/下电的方法。 在上电期间，向连接到扬声器的每个输出端提供预偏置电压以将电压增加到额定输出电平。 然后以50％占空比驱动高阻抗开关。 输出端的反馈信号被提供给一个伺服控制器，可以对输出电压进行微调。 然后，在四分之一周期的时间，以50％的占空比驱动低阻抗开关。 反馈环路的顺序取决于驱动高阻抗或低阻抗开关中的哪一个。 然后在将要放大的音频信号提供给系统之前，去除预偏置电压。 开关的驱动时序是可编程的。 为了断电，基本上提供了相反的顺序。

公开(公告)号：US20110051833A1

公开(公告)日：2011-03-03

申请号：US12551495

申请日：2009-08-31

申请人： Pallab Midya ,  Patrick L. Rakers ,  William J. Roeckner

发明人： Pallab Midya ,  Patrick L. Rakers ,  William J. Roeckner

IPC分类号： H04L1/02 ,  H04L5/16 ,  H04B1/10

CPC分类号： H04B1/525

摘要： A transceiver mitigates signal leakage into a receive path from a transmit path. A subtraction circuit determines a difference between a receive signal and a compensation signal to produce a compensated receive signal prior to demodulation by a demodulator. An equalizer both amplitude adjusts and phase adjusts orthogonal baseband transmit signals based on the difference from the subtraction circuit to produce the compensation signal. A digital tuning circuit determines at least one amplitude adjust coefficient to be used by the equalizer. The equalizer can have a polarity switch or a variable attenuator or a variable delay.

摘要翻译： 收发信机从发送路径减轻信号泄漏到接收路径。 减法电路确定接收信号和补偿信号之间的差异，以在由解调器解调之前产生经补偿的接收信号。 均衡器两者都基于与减法电路的差异来调整和相位调整正交基带发射信号，产生补偿信号。 数字调谐电路确定要由均衡器使用的至少一个幅度调整系数。 均衡器可以具有极性开关或可变衰减器或可变延迟。

公开(公告)号：US06665338B1

公开(公告)日：2003-12-16

申请号：US09478024

申请日：2000-01-05

申请人： Pallab Midya ,  Patrick L. Rakers ,  William J. Roeckner

发明人： Pallab Midya ,  Patrick L. Rakers ,  William J. Roeckner

IPC分类号： H03K908

CPC分类号： H03F3/217 ,  H03K7/08 ,  H03M5/08

摘要： Embodiments of the present invention deal generally with circuitry and methods for converting a sampled digital signal (32) to a naturally sampled digital signal (34). One embodiment relating to a method includes receiving the sampled digital signal, calculating a duty ratio estimate (33) using feedback (52), and using interpolation (62) to determine the naturally sampled digital signal. Circuitry for converting a sampled digital signal (32) to a naturally sampled digital signal (34) includes a natural sampler, where the natural sampler includes an input to receive the sampled digital signal (32) and an input to receive a feedback signal (52). The natural sampler has an output to provide the naturally sampled digital signal (34). In one embodiment, the natural sampler calculates a duty ratio (33) using the feedback signal (52) and uses interpolation to determine the naturally sampled digital signal (34).

摘要翻译： 本发明的实施例总体上涉及将采样数字信号（32）转换为自然采样的数字信号（34）的电路和方法。 与方法相关的一个实施例包括接收采样的数字信号，使用反馈（52）计算占空比估计（33），并使用内插（62）来确定自然采样的数字信号。 用于将采样数字信号（32）转换为自然采样数字信号（34）的电路包括自然采样器，其中自然采样器包括用于接收采样数字信号（32）的输入端和接收反馈信号（52 ）。 自然采样器具有输出以提供自然采样的数字信号（34）。 在一个实施例中，自然采样器使用反馈信号（52）计算占空比（33），并使用内插来确定自然采样的数字信号（34）。

公开(公告)号：US06965339B2

公开(公告)日：2005-11-15

申请号：US10819644

申请日：2004-04-07

申请人： Pallab Midya ,  Matthew R. Miller ,  Patrick L. Rakers

发明人： Pallab Midya ,  Matthew R. Miller ,  Patrick L. Rakers

IPC分类号： H03M1/12 ,  H03M1/34 ,  H03M3/02

CPC分类号： H03M3/00

摘要： A system and method for analog-to-digital conversion using digital pulse width modulation (PWM) is disclosed. The method and system according to the disclosed invention converts an analog input signal to a digital signal in pulse code modulated (PCM) form. The disclosed invention uses a feedback circuit to perform PWM of the analog input signal. The PWM signal is then decimated to obtain the digital signal in PCM form. The system according to the disclosed invention requires lower operating frequency and dissipates lesser power than prior art systems providing the same sampling frequency and resolution. The operation at a lower frequency is achieved by obtaining two samples from every pulse of the PWM signal; the first sample being obtained from the right duty ratio, and the second sample being obtained form the left duty ratio. Further, the disclosed invention has lesser implementation complexity and higher signal-to-noise ratio than prior art.

摘要翻译： 公开了一种使用数字脉宽调制（PWM）进行模数转换的系统和方法。 根据所公开的发明的方法和系统将模拟输入信号转换成脉冲编码调制（PCM）形式的数字信号。 所公开的发明使用反馈电路来执行模拟输入信号的PWM。 然后抽取PWM信号以获得PCM形式的数字信号。 根据所公开的发明的系统需要更低的工作频率并且消耗比提供相同采样频率和分辨率的现有技术系统更小的功率。 通过从PWM信号的每个脉冲获得两个采样来实现较低频率的操作; 从正确的占空比获得第一个样品，并且从左占空比获得第二个样品。 此外，所公开的发明比现有技术具有较小的实现复杂度和更高的信噪比。

公开(公告)号：US20120252396A1

公开(公告)日：2012-10-04

申请号：US13078502

申请日：2011-04-01

申请人： Haolu Xie ,  Manish N. Shah ,  Patrick L. Rakers

发明人： Haolu Xie ,  Manish N. Shah ,  Patrick L. Rakers

IPC分类号： H04B1/16 ,  H03K17/16

CPC分类号： H04B1/28 ,  H03D2200/0074 ,  H03D2200/0088 ,  H03K2217/0054

摘要： A technique for improving the linearity of a mixer is disclosed. A converter may include a mixer comprising a first metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a first conducting terminal coupled to an input of the converter, and a second conducting terminal coupled to an output of the converter, and a mixer driver having a first output coupled to the gate of the first MOSFET, the mixer driver configured to receive a local-oscillator signal having a first phase and a second phase, drive the first MOSFET off during the first phase of the local-oscillator signal, drive the first MOSFET on for a first period of time in response to a transition from the first phase of the local-oscillator signal to the second phase of the local-oscillator signal, and force the gate of the first MOSFET into a high impedance state for a second period of time during the second phase of the local-oscillator signal and after the expiration of the first period of time.

摘要翻译： 公开了一种改善混频器线性度的技术。 A转换器可以包括混合器，其包括具有栅极的第一金属氧化物半导体场效应晶体管（MOSFET），耦合到转换器的输入端的第一导电端子和耦合到转换器的输出端的第二导通端子，以及 混频器驱动器，其具有耦合到第一MOSFET的栅极的第一输出，混频器驱动器被配置为接收具有第一相位和第二相位的本地振荡器信号，在本机振荡器的第一阶段期间驱动第一MOSFET关断 信号，响应于从本地振荡器信号的第一相到本地振荡器信号的第二相的转变，驱动第一MOSFET导通第一时间段，并迫使第一MOSFET的栅极变为高电平 在本地振荡器信号的第二阶段期间和在第一时间段到期之后的第二时间段的阻抗状态。

公开(公告)号：US07706765B2

公开(公告)日：2010-04-27

申请号：US09981476

申请日：2001-10-17

申请人： Timothy James Collins ,  Richard Stanley Rachwalski ,  Patrick L. Rakers ,  David P. Gurney ,  Stephen L. Kuffner

发明人： Timothy James Collins ,  Richard Stanley Rachwalski ,  Patrick L. Rakers ,  David P. Gurney ,  Stephen L. Kuffner

IPC分类号： H04L12/413 ,  H04L12/407

CPC分类号： H04L12/413

摘要： A source device (110) receives a carrier signal and continuously monitors the carrier signal for a first predetermined condition and a second predetermined condition. The source device (110) transmits data if the first predetermined condition is satisfied. The source device (110) ceases transmission of data if the first predetermined condition subsequently is not satisfied or if a second predetermined condition is satisfied.

摘要翻译： 源设备（110）接收载波信号并连续地监视载波信号的第一预定条件和第二预定条件。 如果满足第一预定条件，则源装置（110）发送数据。 如果第一预定条件不满足或满足第二预定条件，则源设备（110）停止数据传输。

公开(公告)号：US07653678B2

公开(公告)日：2010-01-26

申请号：US11457380

申请日：2006-07-13

申请人： Michael L. Bushman ,  Neal W. Hollenbeck ,  Patrick L. Rakers

发明人： Michael L. Bushman ,  Neal W. Hollenbeck ,  Patrick L. Rakers

IPC分类号： G06G7/16

CPC分类号： G06G7/26

摘要： A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.

摘要翻译： 直接数字合成电路（108）包括多个电流源（210,211,212），输出电路（200）和逻辑乘法器电路（202）。 输出电路（200）提供输出的合成波形（164），并包括第一分支（206）和第二分支（208）。 逻辑乘法器电路（202）可操作地耦合到多个电流源（210,211,212）和输出电路（200）。 逻辑乘法器电路（202）可操作以接收多个信号。 逻辑乘法器电路还可操作以选择性地将通过第一分支（206）的第一电流流过确定的幅度，并且基于多个信号减少通过第二分支（208）的确定的幅度的第二电流。 合成波形（164）基于第一和第二电流。

公开(公告)号：US06317755B1

公开(公告)日：2001-11-13

申请号：US09360571

申请日：1999-07-26

申请人： Patrick L. Rakers ,  Timothy James Collins ,  Daniel J. Russell ,  Sam DiRaimondo

发明人： Patrick L. Rakers ,  Timothy James Collins ,  Daniel J. Russell ,  Sam DiRaimondo

IPC分类号： G06F1730

CPC分类号： G07F7/1008 ,  G06F11/1441 ,  G06Q20/341 ,  G06Q20/3576 ,  Y10S707/99955

摘要： A portable data device (300) having a memory (302) is provided. The memory (302) is segmented into a plurality of sectors (304-312). A backup memory buffer (312) and a plurality of applications (304-310) are programmed into the plurality of sectors, wherein the backup memory buffer (312) is jointly used by the plurality of applications (304-310). A valid state of data is stored in the backup memory buffer (312) prior to performing a transaction for a first application (304). The valid state of data is restored in the first application (304) upon power up of the portable data device (300) in an event the transaction is terminated prior to completion, wherein the step of restoring is independent of a next application in which a next transaction is performed.

摘要翻译： 提供具有存储器（302）的便携式数据设备（300）。 存储器（302）被分割成多个扇区（304-312）。 备份存储器缓冲器（312）和多个应用程序（304-310）被编程到多个扇区中，其中备用存储器缓冲器（312）由多个应用程序共同使用（304-310）。 在对第一应用执行交易之前，将有效的数据状态存储在备份存储器缓冲器（312）中（304）。 在事务在完成之前被终止的情况下，在便携式数据设备（300）上电时，在第一应用（304）中恢复数据的有效状态，其中恢复步骤独立于下一个应用 执行下一个事务。

公开(公告)号：US08698664B2

公开(公告)日：2014-04-15

申请号：US13363884

申请日：2012-02-01

申请人： Omid Oliaei ,  Patrick L. Rakers

发明人： Omid Oliaei ,  Patrick L. Rakers

IPC分类号： H03M1/12

CPC分类号： H03M3/45 ,  H03M3/454

摘要： In accordance with embodiments of the present disclosure, a continuous-time incremental analog-to-digital converter (ADC) may include a plurality of resettable integrators and a feed-in gain element. Each integrator may be configured to convert a sum of signals received at its input to a signal indicative of an integral over time of the sum of signals. The plurality of integrators may include a first-stage integrator configured to receive at its input the baseband signal and a final-stage integrator configured to produce at its output a final-stage analog signal. The plurality of integrators may be arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator. The feed-in gain element may be coupled between the input of the first-stage integrator and the input of another integrator of the plurality of integrators.

摘要翻译： 根据本公开的实施例，连续时间增量模数转换器（ADC）可以包括多个可复位积分器和馈入增益元件。 每个积分器可以被配置为将在其输入处接收的信号的和转换成指示信号总和的积分的信号。 多个积分器可以包括被配置为在其输入处接收基带信号的第一级积分器和被配置为在其输出端产生最终级模拟信号的最终级积分器。 多个积分器可以被布置成级联配置，使得除了最终级积分器之外的多个积分器中的每一个的输出耦合到后续积分器的输入。 馈入增益元件可以耦合在第一级积分器的输入端和多个积分器的另一个积分器的输入端之间。

公开(公告)号：US08447246B2

公开(公告)日：2013-05-21

申请号：US13207786

申请日：2011-08-11

申请人： Omid Oliaei ,  David Newman ,  Benjamin Gilsdorf ,  Patrick L. Rakers

发明人： Omid Oliaei ,  David Newman ,  Benjamin Gilsdorf ,  Patrick L. Rakers

IPC分类号： H04B1/04

CPC分类号： H03D7/1441 ,  H03D7/1458 ,  H03D2200/0023 ,  H04B1/0057 ,  H04B1/0483

摘要： In accordance with some embodiments of the present disclosure, a multi-band transmitter comprises a plurality of band paths with each band path configured for a different frequency range. Each band path comprises a modulator configured to modulate a data signal onto a carrier signal associated with the frequency range of the band path to generate a radio frequency (RF) signal associated with the band path and frequency range of the band path. Each band path also comprises a step-down balun that includes an input coil configured to receive the RF signal from the modulator. Each band path further comprises a tuner configured to tune the input coil to the frequency range of the band path. The tuner is also configured to compensate for off-state conduction of switches of the tuner to reduce non-linear tuning effects of the balun associated with the off-state conduction.

摘要翻译： 根据本公开的一些实施例，多频带发射机包括多个频带路径，每个频带路径被配置用于不同的频率范围。 每个频带路径包括被配置为将数据信号调制到与频带路径的频率范围相关联的载波信号上以产生与频带路径的频带路径和频带范围相关联的射频（RF）信号的调制器。 每个频带路径还包括降压平衡 - 不平衡变压器，其包括被配置为从调制器接收RF信号的输入线圈。 每个频带路径还包括被配置为将输入线圈调谐到频带路径的频率范围的调谐器。 调谐器还被配置为补偿调谐器的开关的截止状态传导，以减少与断开状态传导相关联的平衡 - 不平衡变换器的非线性调谐效应。