公开(公告)号：US20200036931A1

公开(公告)日：2020-01-30

申请号：US16491555

申请日：2018-02-27

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yutaka ABE ,  Kazuko NISHIMURA ,  Hiroshi FUJINAKA ,  Masahiro HIGUCHI ,  Dai ICHIRYU

IPC: H04N5/3745 ,  H03M1/56 ,  H03M1/38 ,  H04N5/378

Abstract: A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.

公开(公告)号：US20160142661A1

公开(公告)日：2016-05-19

申请号：US15003410

申请日：2016-01-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Sanshiro SHISHIDO ,  Masahiro HIGUCHI

IPC: H04N5/365 ,  H04N5/369 ,  H03M1/12 ,  H04N5/378

CPC classification number: H04N5/3658 ,  H03M1/1245 ,  H04N5/357 ,  H04N5/3651 ,  H04N5/3698 ,  H04N5/3742 ,  H04N5/37455 ,  H04N5/378

Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.

公开(公告)号：US20160014363A1

公开(公告)日：2016-01-14

申请号：US14858481

申请日：2015-09-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takayasu KITO ,  Hiroyuki AMIKAWA ,  Masahiro HIGUCHI ,  Kenichi ORIGASA ,  Hiroshi FUJINAKA

IPC: H04N5/374 ,  H04N5/347 ,  H04N5/369 ,  H04N5/357 ,  H04N5/378

CPC classification number: H04N5/374 ,  H04N5/3577 ,  H04N5/3698 ,  H04N5/3745 ,  H04N5/378

Abstract: A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.

Abstract translation: 固态成像装置包括：多个单位电池，每个单元电池包括至少一个光接收单元和放大晶体管，其输出对应于由光接收单元光电转换的信号电荷的量的放大信号; 多个垂直信号线，各自用于接收来自放大晶体管的输出信号; 用于向放大晶体管提供电源电压的像素电源线; 多个恒流源晶体管，每个连接到所述垂直信号线中的不同的一个; 以及偏置电路，其基于电源电压的变化来控制要提供给每个恒流源晶体管的电流量。

公开(公告)号：US20150077610A1

公开(公告)日：2015-03-19

申请号：US14554005

申请日：2014-11-25

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Sanshiro SHISHIDO ,  Masahiro HIGUCHI

IPC: H04N5/374 ,  H04N5/357 ,  H04N5/3745 ,  H04N5/378

CPC classification number: H04N5/3658 ,  H03M1/1245 ,  H04N5/357 ,  H04N5/3651 ,  H04N5/3698 ,  H04N5/3742 ,  H04N5/37455 ,  H04N5/378

Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.

Abstract translation: 固态成像装置包括产生用于A / D转换的参考电压的D / A转换电路。 D / A转换电路包括：电压产生电路，根据数字信号产生模拟电压; 缓冲电路，缓冲所产生的模拟电压的缓冲电路，缓冲电路采样并保持在缓冲电路内产生的偏置电压，并使用保持的偏置电压输出缓冲的模拟电压; 模拟信号输出单元（电阻梯形单元），通过接收来自缓冲电路的输出，根据输入的数字信号输出参考电压; 以及与缓冲电路的采样和保持相结合对降噪电容器充电的预充电放大器，降噪电容器连接到模拟信号输出单元。

公开(公告)号：US20150076325A1

公开(公告)日：2015-03-19

申请号：US14552446

申请日：2014-11-24

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Masahiro HIGUCHI ,  Hiroshi FUJINAKA ,  Makoto IKUMA

IPC: H03K4/90 ,  H01L27/146

CPC classification number: H03K4/90 ,  H01L27/14645 ,  H03K4/08 ,  H04N5/357 ,  H04N5/378

Abstract: A ramp generator circuit includes: a reference signal generator circuit which generates a ramp waveform having a slope obtained by multiplication using a power of 2 according to a value of a higher order bit of a gain control signal; a clock control circuit which selectively outputs 2̂m kinds of fractional-N clocks according to one of 2̂m (natural number) areas obtained by dividing a code range represented by a lower order bit, when a negative gain is set; and a variable gain circuit which sets a ramp waveform according to the value of the gain control signal, and sets a ramp signal amplitude in each area so that a period ratio between ramp driving clocks for adjacent areas and a ratio between an amplitude of a ramp signal when the standard gain is set and a largest amplitude of a ramp signal are equal.

Abstract translation: 斜坡发生器电路包括：参考信号发生器电路，其产生具有根据增益控制信号的较高阶位的值使用2的幂乘以获得的斜率的斜坡波形; 时钟控制电路，当设置负增益时，根据通过划分由低位位表示的代码范围获得的2m（自然数）区域中的一个选择性地输出2m种分数N个时钟; 以及可变增益电路，其根据增益控制信号的值设定斜坡波形，并且设置每个区域中的斜坡信号振幅，使得相邻区域的斜坡驱动时钟之间的周期比和斜坡幅度之间的比率 当标准增益被设置并且斜坡信号的最大振幅相等时发出信号。