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1.发明授权公开(公告)号：US06750716B2
公开(公告)日：2004-06-15
申请号：US10162430
申请日：2002-06-03
IPC分类号： H03F345
CPC分类号： H03F3/45179 , H03F2203/45028 , H03F2203/45318 , H03F2203/45631
摘要： The amplifier circuit includes at least one amplification branch having an input transistor, an output transistor, having a source terminal connected to the input terminal and a drain terminal connected to a first output terminal, and a gain raising stage, having an input and an output connected to the source terminal and, respectively, to a gate terminal of the output transistor. The amplifier circuit includes, moreover, a compensation capacitor connected between the gate terminal and the drain terminal of the output transistor.
摘要翻译： 该放大器电路包括具有输入晶体管的至少一个放大支路，具有连接到输入端子的源极端子和连接到第一输出端子的漏极端子的输出晶体管以及具有输入和输出的增益提升级 分别连接到源极端子和输出晶体管的栅极端子。 此外，放大器电路还包括连接在输出晶体管的栅极端子和漏极端子之间的补偿电容器。
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公开(公告)号：US06211705B1
公开(公告)日：2001-04-03
申请号：US09145732
申请日：1998-09-02
IPC分类号： H03K5153
CPC分类号： H03K3/356156
摘要： A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a “buffer” and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.
摘要翻译： 描述了一种定时双稳态电路，其包括两个逆变器，每个逆变器的输入连接到另一个的输出，经由“缓冲器”的输出和电路的输入经由受控的电子开关。 逆变器的电源端子通过另外两个受控开关连接到电路的电源端子。 时钟发生器提供定时信号以控制输入开关打开或关闭，并且当输入开关分别断开或闭合时，控制供电开关闭合或断开。 为了在比较频率高的比较器中获得可用于比较器的锁存器，通过在逆变器的电源端子和供电端子之间布置两个另外的电子开关，这两个电子开关由一个定时控制 信号以相对于输入开关闭合的预定延迟而闭合，并在输入开关断开时打开。
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3.发明授权VCO composed of plural ring oscillators and phase lock loop incorporating the VCO 失效VCO由多个环形振荡器和并入VCO的锁相环构成
公开(公告)号：US5864258A
公开(公告)日：1999-01-26
申请号：US846873
申请日：1997-05-01
CPC分类号： H03K3/013 , H03K3/0315 , H03L7/0995 , H03L7/183
摘要： A voltage-controlled oscillator, with high noise rejection of the supply voltage, includes a plurality of delay cells in an odd number N.gtoreq.3, which are connected to form a first ring oscillator and powered by the difference between a supply voltage Vcc and a variable regulating voltage VR. The VCO comprises at least one second ring oscillator formed by a plurality of delay cells in an odd number M.gtoreq.3, at least one of which is also a delay cell of the first oscillator and at least two of which do not belong to the first oscillator. At least one of these two cells is powered by a constant voltage (Vcc), in such a manner that the two oscillators operate at the same frequency and the interaction between the two oscillators introduces a high-frequency negative feedback which has the effect of effectively reducing the noise of the supply voltage Vcc.
摘要翻译： 具有电源电压的高噪声抑制的压控振荡器包括奇数N 3 / = 3中的多个延迟单元，其连接形成第一环形振荡器，并由电源电压Vcc 和可变调节电压VR。 VCO包括由奇数M> / = 3中的多个延迟单元形成的至少一个第二环形振荡器，其中至少一个延迟单元也是第一振荡器的延迟单元，并且其中至少两个不属于 第一个振荡器。 这两个电池中的至少一个由恒定电压（Vcc）供电，使得两个振荡器以相同的频率工作，并且两个振荡器之间的相互作用引入了具有有效效果的高频负反馈 降低电源电压Vcc的噪声。
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公开(公告)号：US5808488A
公开(公告)日：1998-09-15
申请号：US755466
申请日：1996-11-22
CPC分类号： H03K3/356156
摘要： A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a "buffer" and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.
摘要翻译： 描述了一种定时双稳态电路，其包括两个逆变器，每个逆变器的输入连接到另一个的输出，经由“缓冲器”的输出和电路的输入经由受控的电子开关。 逆变器的电源端子通过另外两个受控开关连接到电路的电源端子。 时钟发生器提供定时信号以控制输入开关打开或关闭，并且当输入开关分别断开或闭合时，控制供电开关闭合或断开。 为了在比较频率高的比较器中获得可用于比较器的锁存器，通过在逆变器的电源端子和供电端子之间布置两个另外的电子开关，这两个电子开关由一个定时控制 信号以相对于输入开关闭合的预定延迟而闭合，并在输入开关断开时打开。
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5.发明授权Method of re-establishing the stability of a sigma-delta modulator and a circuit for implementing the method 有权重新建立Σ-Δ调制器的稳定性的方法和实现该方法的电路公开(公告)号：US06489907B2
公开(公告)日：2002-12-03
申请号：US09919509
申请日：2001-07-30
IPC分类号： H03M300
摘要： A method of re-establishing the stability of a sigma-delta modulator having a plurality of integrator stages in cascade and a quantizer, achieving very short resetting times, a bit sequence corresponding to an instability state of the modulator is defined, the bit-stream output by the modulator is monitored to check whether it includes the instability sequence and, if the instability sequence is detected, the last integrator stage is reset and one or more preceding integrator stages are reset, progressively, until the instability sequence is no longer detected.
摘要翻译： 定义了具有级联的多个积分器级的Σ-Δ调制器和量化器的稳定性的方法，实现非常短的复位时间，对应于调制器的不稳定状态的比特序列，比特流 监视调制器的输出以检查其是否包括不稳定性序列，并且如果检测到不稳定性序列，则最后一个积分器级被复位，并且一个或多个先前的积分器级逐步复位，直到不再检测到不稳定序列。
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6.发明授权Switched-capacitor, fully-differential operational amplifier with high switching frequency 有权具有高开关频率的开关电容，全差分运算放大器公开(公告)号：US06417728B1
公开(公告)日：2002-07-09
申请号：US09887508
申请日：2001-06-22
申请人： Andrea Baschirotto , Paolo Cusinato
发明人： Andrea Baschirotto , Paolo Cusinato
IPC分类号： H03F114
CPC分类号： H03F3/45708 , H03F3/45183 , H03F2203/45461 , H03F2203/45511 , H03F2203/45594 , H03F2203/45666
摘要： Fully-differential, switched-capacitor circuit having a first and second input terminal, and including: an operational amplifier having a first and a second differential input, a first and a second output terminal and a bias control terminal; a feedback network, connected between the differential outputs and the input terminals, and having intermediate nodes connected to the differential inputs of the operational amplifier; and a control circuit, including a detection network and an error amplifier. The error amplifier has a first input receiving a desired common-mode voltage, and an output connected to the bias control terminal and supplying a control voltage. The detection network has a first and a second input connected directly, respectively, to the second input terminal of the operational amplifier, and an output connected to a second input of the error amplifier, and supplying a common-mode drive voltage.
摘要翻译： 具有第一和第二输入端的全差分开关电容器电路，包括：具有第一和第二差分输入的运算放大器，第一和第二输出端子和偏置控制端子; 反馈网络，连接在差分输出和输入端之间，并具有连接到运算放大器的差分输入的中间节点; 以及包括检测网络和误差放大器的控制电路。 误差放大器具有接收期望的共模电压的第一输入端和连接到偏置控制端子并提供控制电压的输出。 检测网络具有分别直接连接到运算放大器的第二输入端的第一和第二输入，以及连接到误差放大器的第二输入端的输出端，并提供共模驱动电压。
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公开(公告)号：US06621435B2
公开(公告)日：2003-09-16
申请号：US10001907
申请日：2001-10-24
申请人： Paolo Cusinato , Andrea Baschirotto
发明人： Paolo Cusinato , Andrea Baschirotto
IPC分类号： H03M300
摘要： A method of improving the signal/noise ratio of a sigma-delta modulator during the re-establishment of its stability that includes: defining a bit sequence corresponding to a state of instability of the modulator, monitoring the flow of bits output by the modulator to check whether it contains the instability bit sequence, and resetting the modulator to zero if the instability bit sequence is detected at the output. To ensure a high signal/noise ratio of the modulator even during the detection and re-establishment of stability, the method also includes: delaying the flow of bits output by the modulator at least for the time required to detect the instability bit sequence and modifying the output bit sequence during the delay period by replacing it with a predetermined bit sequence.
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公开(公告)号：US06496066B2
公开(公告)日：2002-12-17
申请号：US09888087
申请日：2001-06-21
IPC分类号： H03F345
CPC分类号： H03F3/45192 , H03F2203/45682
摘要： The present invention refers to a fully differential operational amplifier of the folded cascode type. In one embodiment the fully differential operational amplifier comprises: a differential input stage able to drive a differential output stage; said differential output stage includes a first branch having at least a first and a second transistor, and a second branch having at least a third and a fourth transistor; said first and second branch are coupled to a first and a second voltage source; a feedback circuit of said first, second, third and fourth transistors that is constituted by a single amplifier having four inputs and four outputs, said four inputs taking the voltages present on a terminal of said first, second, third and fourth transistors, and providing voltages to the control elements of said first, second, third and fourth transistors, which voltages depend on the input voltages of said four inputs.
摘要翻译： 本发明涉及折叠共源共栅型的全差分运算放大器。在一个实施例中，全差分运算放大器包括：能够驱动差分输出级的差分输入级; 所述差分输出级包括具有至少第一和第二晶体管的第一分支和具有至少第三和第四晶体管的第二分支; 所述第一和第二分支耦合到第一和第二电压源; 所述第一，第二，第三和第四晶体管的反馈电路由具有四个输入和四个输出的单个放大器构成，所述四个输入端接收存在于所述第一，第二，第三和第四晶体管的端子上的电压，并提供 电压到所述第一，第二，第三和第四晶体管的控制元件，这些电压取决于所述四个输入的输入电压。
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公开(公告)号：US06483449B2
公开(公告)日：2002-11-19
申请号：US09904442
申请日：2001-07-11
IPC分类号： H03M300
CPC分类号： H03M3/502 , H03M7/3022
摘要： A digital-analog converter having a sigma delta cascade modulator with two outputs, particularly a third order sigma delta modulator 2+1. The digital-analog converter includes a sigma delta modulator of the type having two outputs able to supply a first and a second signal to the two outputs; a reconstruction circuit of the first and second signals able to provide a reconstructed signal; a filter able to filter the reconstructed signal; the reconstruction circuit combining the first and second signals according to the following relationship: Yout Y1*(1+Z−1)−Y2*(1−Z−1)+Y2*Z−2*(1−Z−1), where: Yout corresponds to said reconstructed signal, Y1 corresponds to said first signal, Y2 corresponds to said according to signal, Z corresponds to the Z transform.
摘要翻译： 具有具有两个输出的Σ-Δ级联调制器的数模转换器，特别是三阶Σ-Δ调制器2 + 1。 数模转换器包括具有两个能够向两个输出提供第一和第二信号的输出的Σ-Δ调制器; 所述第一和第二信号的重建电路能够提供重建的信号; 能够对重构信号进行滤波的滤波器; 重建电路根据以下关系组合第一和第二信号：其中：Yout对应于所述重构信号，Y1对应于所述第一信号，Y2对应于所述根据信号，Z对应于Z变换。
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公开(公告)号：US06486736B2
公开(公告)日：2002-11-26
申请号：US09802583
申请日：2001-03-08
IPC分类号： H03F345
CPC分类号： H03F3/45264 , H03F3/3061 , H03F3/45273 , H03F2203/45711
摘要： A class AB single-stage operational amplifier having input decoupler stages for voltage signals, a voltage repeater stage, biasing transistors and bias current generators for the input decoupler stages, and capacitors placed between the input decoupler stages and the voltage repeater stage so as to increase the phase margin.
摘要翻译： 具有用于电压信号的输入去耦器级，用于输入去耦器级的电压中继器级，偏置晶体管和偏置电流发生器以及放置在输入解耦器级和电压中继器级之间的电容器的AB类单级运算放大器，以增加 相位裕度。
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