公开(公告)号：US20070164426A1

公开(公告)日：2007-07-19

申请号：US11306982

申请日：2006-01-18

申请人： Patrick McGinnis ,  Darrell Miles ,  Richard Oldrey ,  John Sylvestri ,  Manuel Villalobos

发明人： Patrick McGinnis ,  Darrell Miles ,  Richard Oldrey ,  John Sylvestri ,  Manuel Villalobos

IPC分类号： H01L23/34

CPC分类号： G01R31/2891 ,  G01R31/311

摘要： An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die.

摘要翻译： 一种用于在测试期间实现集成电路冷却的装置和其基于图像的分析，其包括：盖，其被配置为限定集成电路管芯周围的空腔，所述管芯安装到模块基板。 一个或多个流体通道限定在盖内，其中通道有助于冷却液体流过所述空腔并在集成电路管芯上流动，并且在盖内形成透明窗口，以便于观察集成电路管芯 。

公开(公告)号：US20060097742A1

公开(公告)日：2006-05-11

申请号：US10904435

申请日：2004-11-10

申请人： Patrick McGinnis ,  Darrell Miles ,  Richard Oldrey ,  John Sylvestri ,  Manuel Villalobos

发明人： Patrick McGinnis ,  Darrell Miles ,  Richard Oldrey ,  John Sylvestri ,  Manuel Villalobos

IPC分类号： G01R31/26

CPC分类号： G01R31/2886 ,  G01R1/0408 ,  G01R31/311

摘要： An apparatus for facilitating single die backside probing of semiconductor devices includes a chip holder configured for receiving a single integrated circuit die attached thereto, the chip holder maintained in flexible engagement in an X-Y orientation with respect to a lift plate. A lift ring is coupled to the lift plate, the lift ring configured to facilitate adjustment of the lift plate and the chip holder in a Z-direction.

摘要翻译： 用于促进半导体器件的单模背面探测的装置包括芯片保持器，其构造成用于接收附接到其上的单个集成电路管芯，所述芯片保持器相对于升降板以X-Y取向保持柔性接合。 提升环联接到提升板，提升环构造成便于在Z方向上调节提升板和芯片保持器。

公开(公告)号：US20050073333A1

公开(公告)日：2005-04-07

申请号：US10605530

申请日：2003-10-06

申请人： Barbara Averill ,  Terence Kane ,  Darrell Miles ,  Richard Oldrey ,  John Sylvestri

发明人： Barbara Averill ,  Terence Kane ,  Darrell Miles ,  Richard Oldrey ,  John Sylvestri

IPC分类号： G01N1/32 ,  G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2886 ,  G01N1/32 ,  G01R31/2898

摘要： A method for implementing backside probing of a semiconductor device includes isolating an identified defect area on a backside of the semiconductor device, and milling the identified defect area to an initial depth. Edges of the identified defect area are masked, wherein unmasked semiconductor material, beginning at the initial depth, is etched for a plurality of timed intervals until one or more active devices are reached. The one or more active devices are electrically probed.

摘要翻译： 用于实现半导体器件的背面探测的方法包括隔离半导体器件的背面上的识别的缺陷区域，以及将所识别的缺陷区域研磨到初始深度。 所识别的缺陷区域的边缘被掩蔽，其中从初始深度开始的未屏蔽半导体材料被蚀刻多个定时间隔，直到达到一个或多个有源器件。 一个或多个有源器件被电探测。

公开(公告)号：US20060030160A1

公开(公告)日：2006-02-09

申请号：US11242719

申请日：2005-10-03

申请人： Terence Kane ,  Darrell Miles ,  John Sylvestri ,  Michael Tenney

发明人： Terence Kane ,  Darrell Miles ,  John Sylvestri ,  Michael Tenney

IPC分类号： A61N5/00 ,  H01L21/302

CPC分类号： H01J37/32366 ,  G01N1/32 ,  G01R31/2898 ,  H01J2237/3114

摘要： A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.

摘要翻译： 一种用于背面非层叠半导体器件以暴露设备的FEOL半导体特征以用于随后的电和/或物理探测的方法和系统。 在半导体的背面基板层内形成窗口。 产生并引导准直离子等离子体，以便仅通过聚焦屏蔽件中的开口在后侧窗口内接触半导体。 这种聚焦的准直离子等离子体仅在窗口内接触半导体，同时半导体同时被温度控制的阶段旋转和倾斜，以均匀地去除半导体层，使得半导体特征在半导体上对应于 后视窗，曝光。 通过CAIBE处理可以增强本发明的背面未铺层。

公开(公告)号：US20060066325A1

公开(公告)日：2006-03-30

申请号：US10711556

申请日：2004-09-24

申请人： Patrick McGinnis ,  John Sylvestri

发明人： Patrick McGinnis ,  John Sylvestri

IPC分类号： G01R31/302

CPC分类号： G01R31/311

摘要： A technique is described for performing critical parameter analysis (CPA) of a semiconductor device (DUT) by combining the capabilities of conventional automated test equipment (ATE) with a focused optical beam scanning device such as a laser scanning microscope (LSM). The DUT is provided with a fixture such that it can be simultaneously scanned by the LSM or a similar device and exercised by the ATE. The ATE is used to determine pass/fail boundaries of operation of the DUT. Repeatable pass/fail limits (for timing, levels, etc.) are determined utilizing standard test patterns and methodologies. The ATE vector pattern(s) can then be programmed to “loop” the test under a known passing or failing state. When light energy from the LSM scanning beam sufficiently disturbs the DUT to produce a transition (i.e., to push the device outside of its critical parameter limits), this transition is indicated on the displayed image of the DUT, indicating to the user which elements of the DUT were implicated in the transition.

摘要翻译： 描述了通过将常规自动化测试设备（ATE）与诸如激光扫描显微镜（LSM）的聚焦光束扫描设备组合的能力来执行半导体器件（DUT）的关键参数分析（CPA）的技术。 DUT被提供有固定装置，使得它可以被LSM或类似装置同时扫描并由ATE执行。 ATE用于确定DUT的操作的通过/失败边界。 可通过标准测试模式和方法来确定可重复的通过/失败限制（时间，等级等）。 然后可以将ATE矢量图案编程为在已知的通过或失败状态下“循环”测试。 当来自LSM扫描光束的光能充分地扰乱DUT以产生转变（即，将器件推到其关键参数限制之外）时，该转换在DUT的显示图像上指示，向用户指示哪些元素 被试涉及转型。

公开(公告)号：US20060108609A1

公开(公告)日：2006-05-25

申请号：US10904661

申请日：2004-11-22

申请人： Brett Engel ,  Stephen Lucarini ,  John Sylvestri ,  Yun-Yu Wang

发明人： Brett Engel ,  Stephen Lucarini ,  John Sylvestri ,  Yun-Yu Wang

IPC分类号： H01L29/76

CPC分类号： H01L23/3192 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

摘要翻译： 本发明提供一种半导体器件，其包括在半导体衬底顶部的栅极电介质，所述半导体衬底含有邻近栅极电介质的源区和漏区; 栅极电介质顶部的栅极导体; 位于至少栅极导体侧壁上的保形介质钝化堆叠，所述保形介质钝化堆叠包括多个保形介电层，其中没有电路完全穿过堆叠; 以及与源区和漏区的接触，其中通过保形电介质钝化堆的不连续接缝基本上消除了接触和栅极导体之间​​的短路。 本发明还提供了形成上述半导体器件的方法。