公开(公告)号：US20060108609A1

公开(公告)日：2006-05-25

申请号：US10904661

申请日：2004-11-22

申请人： Brett Engel ,  Stephen Lucarini ,  John Sylvestri ,  Yun-Yu Wang

发明人： Brett Engel ,  Stephen Lucarini ,  John Sylvestri ,  Yun-Yu Wang

IPC分类号： H01L29/76

CPC分类号： H01L23/3192 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

摘要翻译： 本发明提供一种半导体器件，其包括在半导体衬底顶部的栅极电介质，所述半导体衬底含有邻近栅极电介质的源区和漏区; 栅极电介质顶部的栅极导体; 位于至少栅极导体侧壁上的保形介质钝化堆叠，所述保形介质钝化堆叠包括多个保形介电层，其中没有电路完全穿过堆叠; 以及与源区和漏区的接触，其中通过保形电介质钝化堆的不连续接缝基本上消除了接触和栅极导体之间​​的短路。 本发明还提供了形成上述半导体器件的方法。

公开(公告)号：US20050285106A1

公开(公告)日：2005-12-29

申请号：US11205522

申请日：2005-08-17

申请人： Terence Kane ,  Chung-Ping Eng ,  Brett Engel ,  Barry Ginsberg ,  Dermott MacPherson ,  John Petrus

发明人： Terence Kane ,  Chung-Ping Eng ,  Brett Engel ,  Barry Ginsberg ,  Dermott MacPherson ,  John Petrus

IPC分类号： G01N21/68 ,  H01L21/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/302 ,  H01L21/461 ,  H01L21/4763 ,  H01L23/58 ,  H01L29/10

CPC分类号： H01L21/67253 ,  G01N21/68 ,  H01J37/32009 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/32131 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of etching a semiconductor structure using ion milling with a variable-position endpoint detector to unlayer multiple interconnect layers, including low-k dielectric films. The ion milling process is controlled for each material type to maintain a planar surface with minimal damage to the exposed materials. In so doing, an ion beam mills a first layer and detects an endpoint thereof using an optical detector positioned within the ion beam adjacent the first layer to expose a second layer of low-k dielectric film. Once the low-k dielectric film is exposed, a portion of the low-k dielectric film may be removed to provide spaces therein, which are backfilled with a material and polished to remove the backfill material and a layer of the multiple interconnect metal layers. Still further, the exposed low-k dielectric film may then be removed, and the exposed metal vias polished.

摘要翻译： 使用可变位置端点检测器使用离子铣削蚀刻半导体结构以使多层互连层（包括低k介电膜）层叠的方法。 对于每种材料类型来控制离子研磨工艺以保持平坦表面，同时对暴露的材料具有最小的损伤。 这样做，离子束研磨第一层并使用位于邻近第一层的离子束内的光学检测器来检测其端点，以暴露第二层低k电介质膜。 一旦露出低k电介质膜，可以去除低k电介质膜的一部分以在其中提供空间，其中填充有材料并被抛光以去除回填材料和多个互连金属层的层。 此外，然后可以去除暴露的低k电介质膜，并且暴露的金属通孔被抛光。

公开(公告)号：US20070099433A1

公开(公告)日：2007-05-03

申请号：US11163909

申请日：2005-11-03

申请人： Brett Engel ,  Dermott MacPherson ,  Aaron Shore

发明人： Brett Engel ,  Dermott MacPherson ,  Aaron Shore

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/31058 ,  H01L21/3105 ,  H01L21/7682 ,  H01L21/76825

摘要： Methods and resulting structure of forming a gas dielectric structure in an interconnect structure are disclosed. In one embodiment, the method includes providing the interconnect structure including at least one interconnect layer having a dielectric, at least one conductor and a first cap layer; and causing the dielectric to contract to form the gas dielectric structure by exposing the interconnect structure to radiation. The radiation can be electron beam radiation or UV radiation. In one embodiment, an interface-breaking enhancing film can be used to selectively locate the gas dielectric structures formed.

摘要翻译： 公开了在互连结构中形成气体电介质结构的方法和结果。 在一个实施例中，该方法包括提供包括具有电介质，至少一个导体和第一盖层的至少一个互连层的互连结构; 并且通过将互连结构暴露于辐射而使电介质收缩以形成气体介质结构。 辐射可以是电子束辐射或紫外线辐射。 在一个实施例中，可以使用界面破坏增强膜来选择性地定位所形成的气体电介质结构。

公开(公告)号：US20060014376A1

公开(公告)日：2006-01-19

申请号：US11230841

申请日：2005-09-20

申请人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

发明人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/31

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。