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公开(公告)号：US08390490B2
公开(公告)日：2013-03-05
申请号：US13106585
申请日：2011-05-12
申请人： Patrick Satarzadeh , Marco Corsi , Victoria Wang , Arthur J. Redfern , Fernando Mujica , Charles Sestok , Kun Shi , Venkatesh Srinivasan
发明人： Patrick Satarzadeh , Marco Corsi , Victoria Wang , Arthur J. Redfern , Fernando Mujica , Charles Sestok , Kun Shi , Venkatesh Srinivasan
IPC分类号： H03M1/12
CPC分类号： H03M1/1265
摘要： Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.
摘要翻译： 压缩感测是一个新兴领域，它试图防止与数据压缩相关的损失，并提高整体效率，压缩感测在能量浪费之前，在捕获之前或捕获过程中会执行压缩。 这里，提供了几个模数转换器（ADC）架构来执行压缩感测。 这些新架构中的每一个基本上随机选择每个样本的分辨率，并根据这些选择的分辨率调整采样率。
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公开(公告)号：US20120286981A1
公开(公告)日：2012-11-15
申请号：US13106585
申请日：2011-05-12
申请人： Patrick Satarzadeh , Marco Corsi , Victoria Wang , Arthur J. Redfern , Fernando Mujica , Charles Sestok , Kun Shi , Venkatesh Srinivasan
发明人： Patrick Satarzadeh , Marco Corsi , Victoria Wang , Arthur J. Redfern , Fernando Mujica , Charles Sestok , Kun Shi , Venkatesh Srinivasan
IPC分类号： H03M1/66
CPC分类号： H03M1/1265
摘要： Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.
摘要翻译： 压缩感测是一个新兴领域，它试图防止与数据压缩相关的损失，并提高整体效率，压缩感测在能量浪费之前，在捕获之前或捕获过程中会执行压缩。 这里，提供了几个模数转换器（ADC）架构来执行压缩感测。 这些新架构中的每一个基本上随机选择每个样本的分辨率，并根据这些选择的分辨率调整采样率。
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3.发明授权公开(公告)号：US08514117B2
公开(公告)日：2013-08-20
申请号：US13229462
申请日：2011-09-09
IPC分类号： H03M3/00
摘要： A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.
摘要翻译： 提供了一种方法和相应的装置。 在操作中，模拟信号与积分器集成以产生集成的模拟信号。 将集成模拟信号与第一时钟信号和第二时钟信号同步地与多个比较器进行参考电压的比较，以产生比较器输出信号。 然后与比较器输出信号产生与第二时钟信号同步的反馈电流。 反馈电流被反馈到比较器中的至少一个，并且比较器输出信号与第一时钟信号同步地锁存以产生锁存的输出信号。 该锁存的输出信号被转换为反馈模拟信号，并且确定模拟信号和反馈模拟信号之间的差。
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公开(公告)号：US08284085B2
公开(公告)日：2012-10-09
申请号：US12899205
申请日：2010-10-06
IPC分类号： H03M3/00
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译： 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。
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公开(公告)号：US20120086589A1
公开(公告)日：2012-04-12
申请号：US12899205
申请日：2010-10-06
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
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6.发明授权公开(公告)号：US08253611B2
公开(公告)日：2012-08-28
申请号：US12899158
申请日：2010-10-06
IPC分类号： H03M1/10
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译： 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。
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7.发明申请公开(公告)号：US20130063291A1
公开(公告)日：2013-03-14
申请号：US13229462
申请日：2011-09-09
摘要： A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.
摘要翻译： 提供了一种方法和相应的装置。 在操作中，模拟信号与积分器集成以产生集成的模拟信号。 将集成模拟信号与第一时钟信号和第二时钟信号同步地与多个比较器进行参考电压的比较，以产生比较器输出信号。 然后与比较器输出信号产生与第二时钟信号同步的反馈电流。 反馈电流被反馈到比较器中的至少一个，并且比较器输出信号与第一时钟信号同步地锁存以产生锁存的输出信号。 该锁存的输出信号被转换为反馈模拟信号，并且确定模拟信号和反馈模拟信号之间的差。
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公开(公告)号：US08970411B2
公开(公告)日：2015-03-03
申请号：US13601795
申请日：2012-08-31
IPC分类号： H03M3/00
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译： 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。
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公开(公告)号：US20120326906A1
公开(公告)日：2012-12-27
申请号：US13601795
申请日：2012-08-31
IPC分类号： H03M3/02
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译： 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。
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公开(公告)号：US20120262319A1
公开(公告)日：2012-10-18
申请号：US13532436
申请日：2012-06-25
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
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