-
1.发明授权公开(公告)号：US08941517B2
公开(公告)日：2015-01-27
申请号：US13532436
申请日：2012-06-25
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译： 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。
-
2.发明申请公开(公告)号：US20130063291A1
公开(公告)日：2013-03-14
申请号：US13229462
申请日：2011-09-09
摘要： A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.
摘要翻译： 提供了一种方法和相应的装置。 在操作中，模拟信号与积分器集成以产生集成的模拟信号。 将集成模拟信号与第一时钟信号和第二时钟信号同步地与多个比较器进行参考电压的比较，以产生比较器输出信号。 然后与比较器输出信号产生与第二时钟信号同步的反馈电流。 反馈电流被反馈到比较器中的至少一个，并且比较器输出信号与第一时钟信号同步地锁存以产生锁存的输出信号。 该锁存的输出信号被转换为反馈模拟信号，并且确定模拟信号和反馈模拟信号之间的差。
-
公开(公告)号：US20130063210A1
公开(公告)日：2013-03-14
申请号：US13229445
申请日：2011-09-09
IPC分类号： H03F3/45
CPC分类号： H03F1/223 , H03F3/45201 , H03F2203/45562 , H03F2203/45644
摘要： For high speed amplifiers, the parasitic capacitances from the differential input pair introduce a zero that can affect performance. Here, a neutralization network has been provided that compensates for this zero by shifting its position. This is generally accomplished by using a pair of capacitors that are cross-coupled across the differential input pair of the amplifier.
摘要翻译： 对于高速放大器，差分输入对的寄生电容引入可影响性能的零。 这里提供了一个中和网络，通过改变其位置来补偿这个零点。 这通常通过使用跨越放大器的差分输入对交叉耦合的一对电容来实现。
-
公开(公告)号：US08390490B2
公开(公告)日：2013-03-05
申请号：US13106585
申请日：2011-05-12
申请人： Patrick Satarzadeh , Marco Corsi , Victoria Wang , Arthur J. Redfern , Fernando Mujica , Charles Sestok , Kun Shi , Venkatesh Srinivasan
发明人： Patrick Satarzadeh , Marco Corsi , Victoria Wang , Arthur J. Redfern , Fernando Mujica , Charles Sestok , Kun Shi , Venkatesh Srinivasan
IPC分类号： H03M1/12
CPC分类号： H03M1/1265
摘要： Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.
摘要翻译： 压缩感测是一个新兴领域，它试图防止与数据压缩相关的损失，并提高整体效率，压缩感测在能量浪费之前，在捕获之前或捕获过程中会执行压缩。 这里，提供了几个模数转换器（ADC）架构来执行压缩感测。 这些新架构中的每一个基本上随机选择每个样本的分辨率，并根据这些选择的分辨率调整采样率。
-
公开(公告)号：US20130015918A1
公开(公告)日：2013-01-17
申请号：US13184131
申请日：2011-07-15
IPC分类号： H03F3/45
CPC分类号： H03F3/45188 , H03F1/0205 , H03F1/086 , H03F2203/45332 , H03F2203/45512
摘要： For high speed amplifiers, the parasitic capacitances between a differential input pairs and a cascoded bias network can introduce a pole that can affect performance. Here, a feedforward network has been provided that compensates for this pole by introducing a zero that effectively cancels the pole, moving the next parasitic without any additional power. This is generally accomplished by using a pair of feedforward capacitors coupled across the transistors of the cascoded bias network, which reduced power consumption.
摘要翻译： 对于高速放大器，差分输入对和级联偏置网络之间的寄生电容可能引入可影响性能的极点。 这里，已经提供了一种前馈网络，通过引入有效地消除极点的零来补偿该极点，移动下一个寄生器而没有任何额外的功率。 这通常通过使用耦合在级联偏压网络的晶体管上的一对前馈电容来实现，这降低了功耗。
-
公开(公告)号：US20120302754A1
公开(公告)日：2012-11-29
申请号：US13378962
申请日：2010-06-18
申请人： Venkatesh Srinivasan , Jennifer Alford , Beth Slusar-Place , Charles Swindell , Michael Horn , Khisal Alvi , Gilbert Gorr
发明人： Venkatesh Srinivasan , Jennifer Alford , Beth Slusar-Place , Charles Swindell , Michael Horn , Khisal Alvi , Gilbert Gorr
IPC分类号： C12P17/18 , C07D491/107 , C12N5/04
CPC分类号： A61K31/4355 , C12P17/188
摘要： The present invention relates to the production of alkaloids from Liliaceae cell culture.
摘要翻译： 本发明涉及从百合科细胞培养物生产生物碱。
-
公开(公告)号：US08258819B2
公开(公告)日：2012-09-04
申请号：US12911456
申请日：2010-10-25
IPC分类号： G11C27/02
CPC分类号： H03K5/2481 , H03K3/356182
摘要： Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths).
摘要翻译： 传统上，锁存的比较器遭受与闩锁暴露到负载电容相关的性能问题。 即使通过电阻将锁存器与负载电容隔离的尝试也导致性能问题（即电压摆幅降低）。 然而，这里提供了一种使用电感器通常提供与负载电容的隔离的锁存比较器，这通常改善了性能。 此外，锁存器已被修改以在轨道周期期间容纳电感器（即，提供接地路径）。
-
8.发明申请公开(公告)号：US20120086590A1
公开(公告)日：2012-04-12
申请号：US12899158
申请日：2010-10-06
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译： 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。
-
9.发明授权公开(公告)号：US08519873B2
公开(公告)日：2013-08-27
申请号：US13229434
申请日：2011-09-09
IPC分类号： H03M1/06
摘要： In higher order sigma-delta modulators (SDMs), there are oftentimes errors introduced by the digital-to-analog (DAC) switches. Namely, parasitic capacitances associated with switches can introduce second harmonic spurs. Here, however, compensation circuits and buffers are provided. The buffers bias the switches in saturation, and the compensation circuits provide a “ground boost” for the buffers. The combination of the buffer and compensation circuit reduces the second harmonic spur, while also improving the Signal-to-Noise Ratio (SNR) and Signal-to-Noise-plus-Distortion Ratio (SNDR).
摘要翻译： 在高阶Σ-Δ调制器（SDM）中，通常由数模转换器（DAC）引入误差。 即，与开关相关的寄生电容可以引入二次谐波杂散。 然而，这里提供补偿电路和缓冲器。 缓冲器将开关偏置在饱和状态，补偿电路为缓冲器提供“接地提升”。 缓冲器和补偿电路的组合减少了二次谐波杂散，同时也提高了信噪比（SNR）和信噪比加失真比（SNDR）。
-
公开(公告)号：US08284085B2
公开(公告)日：2012-10-09
申请号：US12899205
申请日：2010-10-06
IPC分类号： H03M3/00
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译： 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。
-
-
-
-
-
-
-
-
-
搜索结果
43 条记录 (耗时 0.023 秒)
