Method for calibrating a pipelined continuous-time sigma delta modulator
    1.
    发明授权
    Method for calibrating a pipelined continuous-time sigma delta modulator 有权
    校准流水线连续时间Σ-Δ调制器的方法

    公开(公告)号:US08253611B2

    公开(公告)日:2012-08-28

    申请号:US12899158

    申请日:2010-10-06

    IPC分类号: H03M1/10

    摘要: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

    摘要翻译: 传统上,流水线连续时间(CT)Σ-Δ调制器(SDM)已经难以构建,至少部分是由于校准管道的困难。 然而,这里提供了一种流水线CT SDM,其具有有助于被校准的架构。 也就是说,该系统包括数字滤波器和其他可调整的特征,以解决输入不平衡误差以及量化泄漏噪声。

    Method for calbrating a pipelined continuous-time sigma delta modulator
    2.
    发明授权
    Method for calbrating a pipelined continuous-time sigma delta modulator 有权
    用于压缩流水线连续时间Σ-Δ调制器的方法

    公开(公告)号:US08941517B2

    公开(公告)日:2015-01-27

    申请号:US13532436

    申请日:2012-06-25

    IPC分类号: H03M1/10 H03M3/00

    摘要: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

    摘要翻译: 传统上,流水线连续时间(CT)Σ-Δ调制器(SDM)已经难以构建,至少部分是由于校准管道的困难。 然而,这里提供了一种流水线CT SDM,其具有有助于被校准的架构。 也就是说,该系统包括数字滤波器和其他可调整的特征,以解决输入不平衡误差以及量化泄漏噪声。

    METHOD FOR CALBRATING A PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR
    4.
    发明申请
    METHOD FOR CALBRATING A PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR 有权
    用于校准连续连续时间信号调制器的方法

    公开(公告)号:US20120086590A1

    公开(公告)日:2012-04-12

    申请号:US12899158

    申请日:2010-10-06

    IPC分类号: H03M1/10 H03M3/00

    摘要: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

    摘要翻译: 传统上,流水线连续时间(CT)Σ-Δ调制器(SDM)已经难以构建,至少部分是由于校准管道的困难。 然而,这里提供了一种流水线CT SDM,其具有有助于被校准的架构。 也就是说,该系统包括数字滤波器和其他可调整的特征,以解决输入不平衡误差以及量化泄漏噪声。

    PIPELINED ADC INTER-STAGE ERROR CALIBRATION
    7.
    发明申请
    PIPELINED ADC INTER-STAGE ERROR CALIBRATION 有权
    管道ADC内部错误校准

    公开(公告)号:US20120212358A1

    公开(公告)日:2012-08-23

    申请号:US13032457

    申请日:2011-02-22

    IPC分类号: H03M1/06

    摘要: An analog-to-digital converter (ADC) is provided. The ADC includes a plurality of pipelined ADCs and an adjustment circuit. Each pipelined ADC is adapted to receive an analog input signal, has an adjustable transfer function, and includes a compensator. The adjustment circuit is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error.

    摘要翻译: 提供了一个模拟 - 数字转换器(ADC)。 ADC包括多个流水线ADC和调整电路。 每个流水线ADC适于接收模拟输入信号,具有可调节的传递函数,并且包括补偿器。 调整电路耦合到每个流水线ADC,以便能够调整每个流水线ADC的传递函数,以便通常消除估计模糊度。 此外,调节电路估计包括级间增益误差和DAC增益误差中的至少一个的级间误差,并且调整每个流水线ADC的补偿器以补偿级间误差。

    Pipelined ADC inter-stage error calibration
    8.
    发明授权
    Pipelined ADC inter-stage error calibration 有权
    流水线ADC级间误差校准

    公开(公告)号:US08451152B2

    公开(公告)日:2013-05-28

    申请号:US13032457

    申请日:2011-02-22

    IPC分类号: H03M1/06

    摘要: An analog-to-digital converter (ADC) is provided. The ADC includes a plurality of pipelined ADCs and an adjustment circuit. Each pipelined ADC is adapted to receive an analog input signal, has an adjustable transfer function, and includes a compensator. The adjustment circuit is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error.

    摘要翻译: 提供了一个模拟 - 数字转换器(ADC)。 ADC包括多个流水线ADC和调整电路。 每个流水线ADC适于接收模拟输入信号,具有可调节的传递函数,并且包括补偿器。 调整电路耦合到每个流水线ADC,以便能够调整每个流水线ADC的传递函数,以便通常消除估计模糊度。 此外,调节电路估计包括级间增益误差和DAC增益误差中的至少一个的级间误差,并且调整每个流水线ADC的补偿器以补偿级间误差。

    Enhanced channel estimator, method of enhanced channel estimating and an OFDM receiver employing the same
    9.
    发明申请
    Enhanced channel estimator, method of enhanced channel estimating and an OFDM receiver employing the same 有权
    增强信道估计器,增强信道估计方法和采用该方法的OFDM接收机

    公开(公告)号:US20050265490A1

    公开(公告)日:2005-12-01

    申请号:US11136121

    申请日:2005-05-24

    IPC分类号: H04L25/02 H04L27/06 H04L27/26

    摘要: The present invention provides an enhanced channel estimator for use with an orthogonal frequency division multiplex (OFDM) receiver employing scattered pilot channel estimates. In one embodiment, the enhanced channel estimator includes a time interpolation estimator configured to provide time-interpolation channel estimates having at least one image for a portion of carriers having the scattered pilot channel estimates. The enhanced channel estimator also includes a frequency interpolation estimator coupled to the time interpolation estimator and configured to provide frequency-interpolation channel estimates for each carrier based on image suppression through balanced-error filtering.

    摘要翻译: 本发明提供了一种与使用分散导频信道估计的正交频分复用(OFDM)接收机一起使用的增强信道估计器。 在一个实施例中,增强信道估计器包括时间插值估计器,其被配置为提供对具有分散导频信道估计的载波的一部分具有至少一个图像的时间插值信道估计。 增强信道估计器还包括耦合到时间插值估计器并被配置为基于通过平衡误差滤波的图像抑制来为每个载波提供频率插值信道估计的频率内插估计器。

    Method to determine RF circuit antenna impedance
    10.
    发明授权
    Method to determine RF circuit antenna impedance 有权
    确定RF电路天线阻抗的方法

    公开(公告)号:US08750816B2

    公开(公告)日:2014-06-10

    申请号:US13569921

    申请日:2012-08-08

    IPC分类号: H04B17/00

    CPC分类号: H04B17/12

    摘要: A process of estimating an admittance of an RF component using a ladder network with alternating series and parallel components by making three VSWR measurements and computing three admittance circle solutions in the complex admittance plane. The admittances circles are transformed through reference planes of the ladder network to obtain three RF component admittance circles, then estimating the RF component admittance using three nearest intersections of the three RF component admittance circles. Reference planes are defined immediately upstream and immediately downstream of each component of the ladder network. The transforms are performed using lumped parameter models of the series and parallel components of the ladder network.

    摘要翻译: 使用具有交替串联和并联组件的梯形网络来估计RF分量的导纳的过程,通过进行三个VSWR测量并在复导纳平面中计算三个导纳圆解。 通过梯形网络的参考平面转换导纳圆以获得三个RF分量导纳圆,然后使用三个RF分量导纳圆的三个最近的交点来估计RF分量导纳。 参考平面紧紧地定位在梯形网络的每个部件的上游和紧邻的下游。 使用梯形网络的串联和并联组件的集总参数模型来执行变换。