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公开(公告)号：US07266737B2
公开(公告)日：2007-09-04
申请号：US11180416
申请日：2005-07-13
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G01R31/318533 , G11C29/88 , G11C2029/3202
摘要： A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.
摘要翻译： 扫描能够用RAM和关联电路的无缺陷备用元件替换缺陷存储器元件和相关电路的半导体存储器电路，以便在修复RAM之前更换有缺陷的RAM元件。 耦合一组置位/复位锁存器以接收来自存储器元件的信号，以及多路复用器控制电路，其被耦合以从多路复用器接收移位信号和ram_inhibit信号以向多路复用器部件提供特定的输入信号。 当扫描操作开始时，活动时钟信号将设置/复位锁存器设置为ram_inhibit模式，并且阻止存储器元件影响存储器输出锁存器的状态，由此当存储器操作开始时，有源时钟信号将复位置位/复位 锁存到系统模式以使多路复用器将适当的信号从存储器元件传递到输出锁存器，并且备用存储器元件被激活以替换有缺陷的存储器元件。
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公开(公告)号：US20070033459A1
公开(公告)日：2007-02-08
申请号：US11180416
申请日：2005-07-13
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G01R31/318533 , G11C29/88 , G11C2029/3202
摘要： A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.
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公开(公告)号：US20130339808A1
公开(公告)日：2013-12-19
申请号：US13523633
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
发明人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
IPC分类号： G06F11/20
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/08 , G11C2029/1204
摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
摘要翻译： 实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。 实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误 记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置 第二个位线地址。
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4.发明申请DYNAMIC GRADUATED MEMORY DEVICE PROTECTION IN REDUNDANT ARRAY OF INDEPENDENT MEMORY (RAIM) SYSTEMS 有权独立存储器（RAIM）系统的冗余阵列中的动态分级存储器件保护公开(公告)号：US20130191703A1
公开(公告)日：2013-07-25
申请号：US13353879
申请日：2012-01-19
CPC分类号： G06F11/10 , G06F11/1004 , G06F11/1076 , G06F2211/109
摘要： Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.
摘要翻译： 提供了包括多个存储器件的独立存储器（RAIM）系统的冗余阵列中的动态分级存储器件保护。 确定多个存储器件中的第一故障存储器件的第一严重性级别。 第一故障存储设备与用于将第一故障存储设备的位置传送到纠错码（ECC）的标识符相关联。 确定多个存储器件中的第二故障存储器件的第二严重性级别。 确定第二严重性级别高于第一严重性级别。 基于确定第二严重性级别高于第一严重性级别，去除来自第一故障存储器设备的标识符。 基于确定第二严重性级别高于第一严重性级别，将标识符应用于第二故障存储设备。
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公开(公告)号：US08271932B2
公开(公告)日：2012-09-18
申请号：US12823010
申请日：2010-06-24
CPC分类号： G06F11/1008 , G06F11/108
摘要： A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.
摘要翻译： 一种用于使用分层注入方案来验证RAIM / ECC设计的计算机实现的方法，所述分级注入方案包括选择用于生成错误掩码的标记，基于所选择的标记选择固定位掩码，确定是否将错误注入至少一个标记 通道和至少一个通道的标记芯片; 以及当确定时将错误随机地注入所述标记通道和所述至少一个标记芯片中的至少一个中。
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公开(公告)号：US20110320914A1
公开(公告)日：2011-12-29
申请号：US12822503
申请日：2010-06-24
申请人： Luiz C. Alves , Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
发明人： Luiz C. Alves , Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , G06F11/108
摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.
摘要翻译： 在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害 失败。
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公开(公告)号：US20110320869A1
公开(公告)日：2011-12-29
申请号：US12822964
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
CPC分类号： G06F11/1666 , G06F11/1044 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.
摘要翻译： 在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作并启动 至少在存储器通道的第一子集上进行新的操作。 存储器系统能够与存储器通道的第一子集一起操作。
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公开(公告)号：US20110320864A1
公开(公告)日：2011-12-29
申请号：US12822968
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
CPC分类号： G06F11/2053 , G06F11/073 , G06F11/0793 , G06F11/1004 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing in response to the removing any stale data being complete.
摘要翻译： 在包括存储器控制器，与存储器控制器通信的多个存储器通道，配置用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供异构恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于在其他存储器通道执行正常的系统操作时对故障存储器通道执行恢复操作，以使恢复的通道与其它存储器通道重新进入操作模式， 存储操作，用于继续标记恢复的通道以防止陈旧的数据，用于在恢复操作完成之后去除任何陈旧的数据，以及用于去除恢复的通道上的标记，以允许所有存储器通道的正常系统操作， 删除，以响应删除任何陈旧的数据完成。
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9.发明授权Multi nodal computer system and method for handling check stops in the multi nodal computer system 有权多节点计算机系统和多节点计算机系统中检查停止处理方法公开(公告)号：US07996715B2
公开(公告)日：2011-08-09
申请号：US12265137
申请日：2008-11-05
申请人： Karin Rebmann , Dietmar Schmunkamp , Tobias Webel , Thomas E. Gilbert , Timothy G. McNamara , Patrick J. Meaney
发明人： Karin Rebmann , Dietmar Schmunkamp , Tobias Webel , Thomas E. Gilbert , Timothy G. McNamara , Patrick J. Meaney
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F9/544 , G06F11/0709 , Y10S707/99931 , Y10S707/99939 , Y10S707/99943
摘要： A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.
摘要翻译： 一种新的多节点计算机系统，其包括不同类型的芯片所驻留的多个节点。 新的多节点计算机系统的特征在于每个节点有一个时钟芯片，每个时钟芯片仅控制驻留在该节点上的芯片，所述芯片适合于在发生故障的情况下向相关联的时钟芯片发送检查停止请求。 新的检查停止处理方法的特征在于，根据检查停止请求的来源，接收到检查停止请求的时钟芯片启动系统检查停止，节点检查或芯片检查停止。
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10.发明授权公开(公告)号：US07984341B2
公开(公告)日：2011-07-19
申请号：US12036697
申请日：2008-02-25
IPC分类号： G06F11/00
CPC分类号： G06F11/0721 , G06F11/076
摘要： A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, increment the pass counter responsive to determining that all errors have been checked, and clear the error counter responsive to determining that the pass counter is greater than or equal to a pass count threshold value.
摘要翻译： 一种用于处理处理器中的错误的系统，包括：错误计数器，通过计数器和可操作以确定第一错误是否有效的处理部分，响应于确定第一错误是活动的，增加错误计数器，增加通过计数器 响应于确定已经检查了所有错误，并且响应于确定通过计数器大于或等于通过计数阈值来清除错误计数器。
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