公开(公告)号：US07009895B2

公开(公告)日：2006-03-07

申请号：US10814719

申请日：2004-03-31

申请人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald W. Plass

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/806 ,  G11C29/848

摘要： The method described uses a Skip-Over technique which requires a set of muxes at the input and output of a block that is to be repaired. The improved method of implementing I/O redundancy control logic has a minimal impact to both chip area and chip wire tracks. To overcome problems of required real estate usage on a chip that was undesirable enables use of odd and even decoder outputs that can share a single wire track, the same wire being utilizable for both odd and even decoder outputs. In order to implement the decode and carry function as a centralized function, there arises a requirement that logically adjacent decode circuits (decoders connected by a carry signal) should be physically close together to minimize the overhead of the carry wiring. If the decode structure and the mux structure are arranged orthogonal to each other, then each decoder output would require a wire track. The described method however, allows odd and even decoder outputs to share the same wire track. This reduces the number of wire tracks from 1 track per I/O to 1 track per 2 I/Os.

摘要翻译： 所描述的方法使用跳过技术，其需要在待修复的块的输入和输出处的一组复用器。 实现I / O冗余控制逻辑的改进方法对芯片面积和芯片线轨都具有最小的影响。 为了克服在不期望的芯片上所需的房地产使用的问题，可以使用可以共享单个线路的奇数和偶数解码器输出，同样的线可用于奇数和偶数解码器输出。 为了实现作为集中功能的解码和携带功能，出现了逻辑上相邻的解码电路（通过进位信号连接的解码器）应物理上靠近在一起以最小化进位线路开销的要求。 如果解码结构和多路复用结构彼此正交配置，则每个解码器输出将需要线轨。 然而，所描述的方法允许奇数和偶数解码器输出共享相同的线轨道。 这减少了每个I / O从1个磁道到每2个I / O到1个磁道的电线轨迹数量。

公开(公告)号：US06584023B1

公开(公告)日：2003-06-24

申请号：US10043024

申请日：2002-01-09

申请人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald W. Plass

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/848

摘要： An exemplary embodiment of the present invention is a system for implementing a column redundancy scheme for arrays with controls that span multiple data bits. The system includes an array of data bits for receiving data inputs, a spare data bit and a field control input line. Also included in the system is circuitry to separate a field control signal from the field control input line into one or more individual control signals for activating a corresponding data bit in the array or for input to a multiplexor. The system further comprises circuitry to steer around a defective data bit in the array. This circuitry includes: a field control signal multiplexor corresponding to each field control signal; a spare control signal multiplexor to activate the spare data bit; a data multiplexor corresponding to each of the data bits in the array; and a spare data multiplexor to steer one of the data inputs to the spare data bit. The system also includes programmable logic in communication with the field control signal multiplexor, the spare control signal multiplexor, the data multiplexor and the spare data multiplexor to cause the steer around to take place in response to detecting a defective data bit in the array.

摘要翻译： 本发明的示例性实施例是用于对具有跨越多个数据位的控制的阵列实现列冗余方案的系统。 该系统包括用于接收数据输入的数据位阵列，备用数据位和场控制输入线。 还包括在系统中的电路是将场​​控制信号与场控制输入线分离成一个或多个单独的控制信号，用于激活阵列中相应的数据位或输入到多路复用器。 该系统还包括用于控制阵列中的有缺陷的数据位的电路。 该电路包括：对应于每个场控制信号的场控制信号多路复用器; 备用控制信号多路复用器，用于激活备用数据位; 与阵列中的每个数据位相对应的数据多路复用器; 以及备用数据多路复用器，以将数据输入中的一个引导到备用数据位。 该系统还包括与现场控制信号多路复用器，备用控制信号多路复用器，数据多路复用器和备用数据多路复用器通信的可编程逻辑，以响应于检测到阵列中的有缺陷的数据位而引起转向。

公开(公告)号：US07210084B2

公开(公告)日：2007-04-24

申请号：US10413612

申请日：2003-04-14

申请人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Thomas J. Knips ,  Donald Plass

IPC分类号： G11C29/30 ,  G11C29/24

CPC分类号： G11C29/40 ,  G11C11/41

摘要： ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches. The second subsystem further receives ABIST control logic as an input to either: (a). combine array valid bits tag valid inputs to produce valid output, or (b) compare array valid bits with tag valid inputs. The apparatus further includes logical NOR functionality for the outputs of the first and second subsystems.

摘要翻译： 具有集成目录比较逻辑功能的ABIST设备和ABIST错误检测功能。 该装置包括NORs在一起的两个子系统。 第一个子系统用于逐位逻辑地对应阵列有效位和标签有效输入，为匹配产生“0”，为了匹配而产生“1”，逻辑上对位逐次结果产生“1” 如果有任何比特错配，则打。 第二子系统进一步接收ABIST控制逻辑作为输入：（a）。 组合数组有效位​​标签有效输入以产生有效输出，或（b）将数组有效位​​与标签有效输入进行比较。 该装置还包括用于第一和第二子系统的输出的逻辑NOR功能。

公开(公告)号：US07085173B1

公开(公告)日：2006-08-01

申请号：US11054270

申请日：2005-02-09

申请人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

IPC分类号： G11C7/10

CPC分类号： G11C7/1048 ,  G11C7/1078 ,  G11C7/1096

摘要： Embodiments of the invention include a circuit for interfacing local bitlines to a global bitline. The circuit includes an interface line coupled to a local bitline through a local bitline device. A global output device has an input coupled to the interface line and an output coupled to the global bitline. A clamping device is coupled to the interface line, the clamping device coupling the interface line to ground in response to a data in signal. A memory having the circuit is also disclosed.

摘要翻译： 本发明的实施例包括用于将本地位线与全局位线接口的电路。 该电路包括通过本地位线装置耦合到本地位线的接口线。 全局输出设备具有耦合到接口线的输入和耦合到全局位线的输出。 夹紧装置耦合到接口线，夹紧装置响应于信号中的数据将接口线耦合到地。 还公开了一种具有该电路的存储器。

公开(公告)号：US07023759B1

公开(公告)日：2006-04-04

申请号：US11054495

申请日：2005-02-09

申请人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

IPC分类号： G11C8/18

CPC分类号： G11C11/418 ,  G11C8/08 ,  G11C8/18

摘要： A method of generating access signals for a memory array. The method includes receiving a synchronization signal and generating a wordline select signal in response to the synchronization signal. A local precharge signal is generated in response to the synchronization signal. A precharge signal is generated in response to the synchronization signal, the precharge signal being a row signal for regulating memory array read operations. A write signal is generated in response to the synchronization signal, the write signal being a row signal for regulating memory array write operations.

摘要翻译： 一种产生存储器阵列的存取信号的方法。 该方法包括接收同步信号并响应于同步信号产生字线选择信号。 响应于同步信号产生局部预充电信号。 响应于同步信号产生预充电信号，预充电信号是用于调节存储器阵列读取操作的行信号。 响应于同步信号产生写入信号，写入信号是用于调节存储器阵列写入操作的行信号。

公开(公告)号：US20080247245A1

公开(公告)日：2008-10-09

申请号：US12139675

申请日：2008-06-16

申请人： John D. Davis ,  Paul A. Bunce ,  Donald W. Plass ,  Kenneth J. Reyer

发明人： John D. Davis ,  Paul A. Bunce ,  Donald W. Plass ,  Kenneth J. Reyer

IPC分类号： G11C7/22

CPC分类号： G11C11/413 ,  G11C7/18

摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

摘要翻译： 为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。 写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。 选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。 至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。 在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

公开(公告)号：US07233542B2

公开(公告)日：2007-06-19

申请号：US11056048

申请日：2005-02-11

申请人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/16

摘要： A system for generating one or more common address signals for multi-port memory arrays. The system includes circuitry receiving one or more read address signal; circuitry receiving one or more write address signal; circuitry receiving an array clock signal; circuitry receiving one or more enable signal; and circuitry generating the common address signals in response to the enable signal, the array clock signal and one of the read address signal and write address signal.

摘要翻译： 一种用于为多端口存储器阵列产生一个或多个公共地址信号的系统。 该系统包括接收一个或多个读取地址信号的电路; 接收一个或多个写入地址信号的电路; 接收阵列时钟信号的电路; 接收一个或多个使能信号的电路; 以及响应于使能信号，阵列时钟信号和读地址信号和写入地址信号之一产生公共地址信号的电路。

公开(公告)号：US07102944B1

公开(公告)日：2006-09-05

申请号：US11056049

申请日：2005-02-11

申请人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/419

摘要： The invention may comprise circuit for programmable control of a discharge deactivation signal when interfacing local bitlines to a global bitline or other circuit. The invention may also comprise a method for programmable ground circuit control for control of a discharge signal deactivation when interfacing local bitlines to a global bitline via a bitline evaluation discharge device comprising: providing input logic states to inputs of a controller circuit; outputting an adjustable ground value from the controller circuit; and controlling the bitline evaluation discharge device with the adjustable ground value.

公开(公告)号：US07099203B1

公开(公告)日：2006-08-29

申请号：US11057281

申请日：2005-02-11

申请人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

IPC分类号： G11C7/10 ,  G11C11/00

CPC分类号： G11C7/22 ,  G11C2207/2263

摘要： A circuit and a method for writing a binary value to a memory cell are provided. The circuit includes a first field-effect transistor having a first drain, a first drain, and a first gate operably coupled between the first drain and the first source. The first drain is operably coupled to a first memory cell. The first gate configured to receive a first data signal. The circuit further includes a second field-effect transistor having a second drain, a second source, and a second gate operably coupled between the second drain and the second source. The drain source is operably coupled to the first memory cell. The second gate is configured to receive a second data signal. The circuit further includes a first signal inverter having a first input terminal and a first output terminal. The first output terminal is operably coupled to both of the first and second sources. The first signal inverter is configured to output a first control signal on the first output terminal when the first input terminal receives a second control signal. When the first control signal has a second logic level and the first data signal has a first logic level and the second data signal has the second logic level, the first and second field-effect transistors induce the first memory cell to store a first binary value.

摘要翻译： 提供了一种将二进制值写入存储单元的电路和方法。 电路包括具有第一漏极，第一漏极和第一栅极的第一场效应晶体管，其可操作地耦合在第一漏极和第一源极之间。 第一漏极可操作地耦合到第一存储器单元。 第一门被配置为接收第一数据信号。 电路还包括第二场效应晶体管，其具有可操作地耦合在第二漏极和第二源之间的第二漏极，第二源极和第二栅极。 漏源可操作地耦合到第一存储单元。 第二门被配置为接收第二数据信号。 电路还包括具有第一输入端和第一输出端的第一信号反相器。 第一输出端子可操作地耦合到第一和第二源两者。 第一信号反相器被配置为当第一输入端子接收到第二控制信号时，在第一输出端子上输出第一控制信号。 当第一控制信号具有第二逻辑电平且第一数据信号具有第一逻辑电平且第二数据信号具有第二逻辑电平时，第一和第二场效应晶体管感应第一存储器单元以存储第一二进制值 。

公开(公告)号：US07283417B2

公开(公告)日：2007-10-16

申请号：US11054059

申请日：2005-02-09

申请人： John D. Davis ,  Paul A. Bunce ,  Donald W. Plass ,  Kenneth J. Reyer

发明人： John D. Davis ,  Paul A. Bunce ,  Donald W. Plass ,  Kenneth J. Reyer

IPC分类号： G11C8/00

CPC分类号： G11C11/413 ,  G11C7/18

摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

摘要翻译： 为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。 写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。 选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。 至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。 在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。