公开(公告)号：US20070118762A1

公开(公告)日：2007-05-24

申请号：US11598325

申请日：2006-11-12

申请人： Paul Master ,  John Watson

发明人： Paul Master ,  John Watson

IPC分类号： H04L9/00 ,  G06F12/14 ,  H04K1/00 ,  H04L9/32 ,  G06F11/30

CPC分类号： G06F21/73 ,  G06F21/10 ,  G06F21/72 ,  H04L9/0866 ,  H04L2209/12 ,  H04L2209/605 ,  H04L2209/80

摘要： The present invention includes an apparatus, method and system for generating a configuration of an adaptive circuit which is inseparable from selected content. Either the adaptive circuit or encrypted, selected content has a unique identifier. In one of the preferred method and system embodiments in which the adaptive circuit has the unique identifier, a request for the selected content is received, along with the unique identifier, such as by a network server. The selected content is then encrypted, based upon the unique identifier, to form encrypted content. Configuration information for the adaptive circuit, corresponding to the unique identifier and the encrypted content, is generated to form corresponding configuration information. A service provider, such as through a network server, transfers the encrypted content and the corresponding configuration information to the adaptive circuit having the unique identifier, which may then be configured for use of the selected content. As a consequence, the present invention creates adaptive hardware configurations which are uniquely coupled to the selected content.

摘要翻译： 本发明包括用于生成与选定内容不可分离的自适应电路的配置的装置，方法和系统。 自适应电路或加密的所选择的内容都具有唯一的标识符。 在其中自适应电路具有唯一标识符的优选方法和系统实施例之一中，接收对所选内容的请求以及诸如网络服务器的唯一标识符。 然后，基于唯一标识符对所选择的内容进行加密，以形成加密的内容。 产生对应于唯一标识符和加密内容的自适应电路的配置信息，以形成对应的配置信息。 诸如通过网络服务器的服务提供商将加密的内容和相应的配置信息传送到具有唯一标识符的自适应电路，然后可以将其配置为使用所选择的内容。 因此，本发明创建独特地耦合到所选内容的自适应硬件配置。

公开(公告)号：US20060080532A1

公开(公告)日：2006-04-13

申请号：US11282460

申请日：2005-11-19

申请人： Paul Master ,  John Watson

发明人： Paul Master ,  John Watson

IPC分类号： H04L9/00

CPC分类号： G06F21/73 ,  G06F21/10 ,  G06F21/72 ,  H04L9/0866 ,  H04L2209/12 ,  H04L2209/605 ,  H04L2209/80

摘要： The present invention includes an apparatus, method and system for generating a configuration of an adaptive circuit which is inseparable from selected content. Either the adaptive circuit or encrypted, selected content has a unique identifier. In one of the preferred method and system embodiments in which the adaptive circuit has the unique identifier, a request for the selected content is received, along with the unique identifier, such as by a network server. The selected content is then encrypted, based upon the unique identifier, to form encrypted content. Configuration information for the adaptive circuit, corresponding to the unique identifier and the encrypted content, is generated to form corresponding configuration information. A service provider, such as through a network server, transfers the encrypted content and the corresponding configuration information to the adaptive circuit having the unique identifier, which may then be configured for use of the selected content. As a consequence, the present invention creates adaptive hardware configurations which are uniquely coupled to the selected content.

公开(公告)号：US20060031660A1

公开(公告)日：2006-02-09

申请号：US11241009

申请日：2005-09-30

申请人： Paul Master ,  Stephen Smith ,  John Watson

发明人： Paul Master ,  Stephen Smith ,  John Watson

IPC分类号： G06F15/00

CPC分类号： G06F15/80 ,  G06F7/57 ,  G06F9/44505 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

摘要翻译： 本发明涉及用于自适应计算的新类别的集成电路的配置。 各种实施例提供用于自适应计算引擎（ACE）集成电路的可执行信息模块，并且可以包括配置信息，操作数数据，并且还可以包括路由和功率控制信息。 ACE IC包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络用于为多个不同的功能模式配置多个异构计算元件。

公开(公告)号：US06795686B2

公开(公告)日：2004-09-21

申请号：US10010596

申请日：2001-12-05

申请人： Paul Master ,  John Watson

发明人： Paul Master ,  John Watson

IPC分类号： H04B715

CPC分类号： H04B7/2609

摘要： Aspects of a method and system for increasing availability and proximity of base stations for cellular communications are provided. The aspects include providing a mobile base station as a feature of a motor vehicle. Adaptive capabilities within the mobile base station are utilized for compatibility with a mobile phone. Cellular communications are performed with the mobile phone via the mobile base station.

摘要翻译： 提供了用于增加用于蜂窝通信的基站的可用性和接近度的方法和系统的方面。 这些方面包括提供作为机动车辆的特征的移动基站。 利用移动基站内的自适应能力与移动电话兼容。 通过移动基站与移动电话执行蜂窝通信。

公开(公告)号：US20070226433A1

公开(公告)日：2007-09-27

申请号：US11803998

申请日：2007-05-16

申请人： Frederick Furtek ,  Paul Master

发明人： Frederick Furtek ,  Paul Master

IPC分类号： G06F12/00

CPC分类号： G06F15/167 ,  G06F3/0626 ,  G06F3/0661 ,  G06F3/0679 ,  G06F13/1657 ,  G11C7/1072 ,  H04L67/32

摘要： A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

公开(公告)号：US20070162268A1

公开(公告)日：2007-07-12

申请号：US11331565

申请日：2006-01-12

申请人： Bhaskar Kota ,  Paul Master ,  Robert Barker ,  Robert Plunkett

发明人： Bhaskar Kota ,  Paul Master ,  Robert Barker ,  Robert Plunkett

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5045

摘要： A computing system and method are provided for algorithmic electronic system level design. An exemplary system comprises a plurality of databases for storing a plurality of functional models, a plurality of computational element models, and a plurality of hardware definition representations. An application design processor is adapted to perform a first functional simulation of an algorithm using a plurality of computational element architecture definitions to generate a first selection of a plurality of computational elements and corresponding control code for an implementation of the algorithm. A control and memory modeling processor is adapted to generate a plurality of flow transforms from the algorithm and to convert the plurality of flow transforms into the plurality of plurality of computational element models. A system simulation processor is adapted to convert the plurality of computational element models into the plurality of hardware definition representations and to perform a second functional simulation of the algorithm using the plurality of computational element models corresponding to the first selection and the corresponding control code.

摘要翻译： 提供了一种用于算法电子系统级设计的计算系统和方法。 示例性系统包括用于存储多个功能模型，多个计算元素模型和多个硬件定义表示的多个数据库。 应用设计处理器适于使用多个计算元素架构定义来执行算法的第一功能仿真，以生成多个计算元件的第一选择以及用于该算法的实现的相应控制代码。 控制和存储器建模处理器适于从所述算法生成多个流变换并将所述多个流变换转换成所述多个计算元素模型。 系统模拟处理器适于将多个计算元素模型转换成多个硬件定义表示，并且使用对应于第一选择和相应控制代码的多个计算元素模型来执行算法的第二功能模拟。

公开(公告)号：US08843928B2

公开(公告)日：2014-09-23

申请号：US13011763

申请日：2011-01-21

申请人： Paul Master ,  Frederick Furtek

发明人： Paul Master ,  Frederick Furtek

IPC分类号： G06F9/46 ,  G06F9/45 ,  G06F15/76 ,  G06F9/40 ,  G06F15/173 ,  G06F9/50

CPC分类号： G06F9/3885 ,  G06F9/4881 ,  G06F9/5033 ,  G06F9/505 ,  G06F15/17362

摘要： A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores stream-domain code including a stream defining a stream destination module and a stream source module. The stream source module places data values in the stream and the stream conveys data values from the stream source module to the stream destination module. A runtime system detects when the data values are available to the stream destination module and schedules the stream destination module for execution on one of the plurality of processing cores.

摘要翻译： 一种多处理核心设备的高效使用和编程方法和系统。 该系统包括基于流域代码的编程结构。 公开了一种基于可编程内核的计算设备。 计算设备包括彼此耦合的多个处理核心。 存储器存储流域代码，包括定义流目的地模块和流源模块的流。 流源模块将数据值放入流中，流将数据流从流源模块传送到流目的地模块。 运行时系统检测数据值何时可用于流目的地模块并且调度流目的地模块以在多个处理核心之一上执行。

公开(公告)号：US20120036514A1

公开(公告)日：2012-02-09

申请号：US13204164

申请日：2011-08-05

申请人： Paul Master ,  Frederick Furtek

发明人： Paul Master ,  Frederick Furtek

IPC分类号： G06F9/50

CPC分类号： G06F8/45 ,  G06F8/456 ,  G06F8/54 ,  G06F9/38 ,  G06F9/445

摘要： A method and system of compiling and linking source stream programs for efficient use of multi-node devices. The system includes a compiler, a linker, a loader and a runtime component. The process converts a source code stream program to a compiled object code that is used with a programmable node based computing device having a plurality of processing nodes coupled to each other. The programming modules include stream statements for input values and output values in the form of sources and destinations for at least one of the plurality of processing nodes and stream statements that determine the streaming flow of values for the at least one of the plurality of processing nodes. The compiler converts the source code stream based program to object modules, object module instances and executables. The linker matches the object module instances to at least one of the multiple cores. The loader loads the tasks required by the object modules in the nodes and configure the nodes matched with the object module instances. The runtime component runs the converted program.

摘要翻译： 编译和链接源流程序以有效利用多节点设备的方法和系统。 该系统包括编译器，链接器，加载器和运行时组件。 该过程将源代码流程序转换为与具有彼此耦合的多个处理节点的基于可编程节点的计算设备一起使用的编译对象代码。 编程模块包括用于多个处理节点和流语句中的至少一个的源和目的地形式的输入值和输出值的流语句，其确定多个处理节点中的至少一个处理节点的值的流式流 。 编译器将基于源代码流的程序转换为对象模块，对象模块实例和可执行文件。 链接器将对象模块实例与多个核心中的至少一个进行匹配。 加载器加载节点中对象模块所需的任务，并配置与对象模块实例匹配的节点。 运行时组件运行转换的程序。

公开(公告)号：US20070271440A1

公开(公告)日：2007-11-22

申请号：US11803997

申请日：2007-05-16

申请人： Paul Master ,  W. Scheuermann

发明人： Paul Master ,  W. Scheuermann

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/223 ,  G06F9/30145 ,  G06F9/325

摘要： A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.

摘要翻译： 一种微处理器架构，包括与用于执行微指令的微代码指令高速缓存组合的有限状态机。 通常会导致高重复循环操作的小序列的微指令在有限状态机（FSM）中实现。 使用FSM比缓存或寄存器集中的循环指令更节能。 此外，在执行微代码指令时，缓存或其他面向内存的方法的灵活性仍然可用。 通过ID标签将微指令识别为FSM操作（与高速缓存操作相反）。 微指令的其他领域可用于识别要使用的FSM电路的类型，直接配置FSM以实现微指令，指示某些字段将在一个或多个FSM和/或面向内存的操作中实现，例如 如缓存或注册。

公开(公告)号：US20110179252A1

公开(公告)日：2011-07-21

申请号：US13011763

申请日：2011-01-21

申请人： Paul Master ,  Frederick Furtek

发明人： Paul Master ,  Frederick Furtek

IPC分类号： G06F15/76 ,  G06F9/06

CPC分类号： G06F9/3885 ,  G06F9/4881 ,  G06F9/5033 ,  G06F9/505 ,  G06F15/17362

摘要： A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores stream-domain code including a stream defining a stream destination module and a stream source module. The stream source module places data values in the stream and the stream conveys data values from the stream source module to the stream destination module. A runtime system detects when the data values are available to the stream destination module and schedules the stream destination module for execution on one of the plurality of processing cores.

摘要翻译： 一种多处理核心设备的高效使用和编程方法和系统。 该系统包括基于流域代码的编程结构。 公开了一种基于可编程内核的计算设备。 计算设备包括彼此耦合的多个处理核心。 存储器存储流域代码，包括定义流目的地模块和流源模块的流。 流源模块将数据值放入流中，流将数据流从流源模块传送到流目的地模块。 运行时系统检测数据值何时可用于流目的地模块并且调度流目的地模块以在多个处理核心之一上执行。