公开(公告)号：US07157795B1

公开(公告)日：2007-01-02

申请号：US10934511

申请日：2004-09-07

申请人： Darrell M. Erb ,  Steven C. Avanzino ,  Christy Mei-Chu Woo

发明人： Darrell M. Erb ,  Steven C. Avanzino ,  Christy Mei-Chu Woo

IPC分类号： H01L23/48

CPC分类号： H01L21/2855 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  Y10S438/927

摘要： Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å.

摘要翻译： 通过在镶嵌Cu的上表面上形成包含氮化钽层的复合顶盖层和氮化钛层上的α-Ta层，显着降低了铜互连的电迁移和应力迁移。 实施例包括在介电层中嵌入的Cu的上表面的上表面中形成凹陷，沉积厚度为的厚度为的二氧化钛层，然后沉积厚度为200埃的α-Ta层 Å至500Å。

公开(公告)号：US06727592B1

公开(公告)日：2004-04-27

申请号：US10079515

申请日：2002-02-22

申请人： Christy Mei-Chu Woo ,  John E. Sanchez ,  Darrell M. Erb ,  Amit P. Marathe

发明人： Christy Mei-Chu Woo ,  John E. Sanchez ,  Darrell M. Erb ,  Amit P. Marathe

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76868 ,  H01L21/76871 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.

摘要翻译： Cu互连，例如 通过在开口中沉积阻挡层通过CVD沉积形成具有改善的电迁移阻力并通过链产量增加的双镶嵌结构，通过PVD沉积α-Ta的闪光层，厚度小于30埃 阻挡层，沉积种子层，然后用Cu填充开口。 实施方案包括沉积厚度小于的薄的α-Ta层和/或沉积在开口侧面上的原子簇的不连续区域。

公开(公告)号：US07071564B1

公开(公告)日：2006-07-04

申请号：US10791904

申请日：2004-03-04

申请人： Darrell M. Erb ,  Steven Avanzino ,  Christy Mei-Chu Woo

发明人： Darrell M. Erb ,  Steven Avanzino ,  Christy Mei-Chu Woo

IPC分类号： H01L29/40 ,  H01L23/12

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： The electromigration and stress migration of Cu interconnects is significantly reduced by forming a composite capping layer comprising a layer of β-Ta on the upper surface of the inlaid Cu, a layer of tantalum nitride on the β-Ta layer and a layer of α-Ta on the tantalum nitride layer. Embodiments include forming a recess in an upper surface of Cu inlaid in a dielectric layer, depositing a layer of β-Ta at a thickness of 25 Å to 40 Å, depositing a layer of tantalum nitride at a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å. Embodiments further include forming an overlying dielectric layer, forming an opening therein, e.g., a via opening or a dual damascene opening, lining the opening with α-Ta, and filling the opening with Cu in electrical contact with the underlying inlaid Cu.

摘要翻译： 通过在嵌入的Cu的上表面上形成包含β-Ta层的复合顶盖层，β-Ta层上的氮化钽层和α-Ta层的一层复合覆盖层，显着降低了铜互连的电迁移和应力迁移， Ta在氮化钽层上。 实施例包括在介电层中嵌入的Cu的上表面中形成凹陷，沉积厚度为的Å-Ta层，沉积厚度为Å至100埃的氮化钽层，以及 然后沉积厚度为200埃至500埃的α-Ta层。 实施例还包括形成覆盖的介电层，在其中形成开口，例如通孔开口或双镶嵌开口，用α-Ta衬套开口，以及用与电镀底层Cu接触的Cu填充开口。

公开(公告)号：US06979625B1

公开(公告)日：2005-12-27

申请号：US10704595

申请日：2003-11-12

申请人： Christy Mei-Chu Woo ,  Connie Pin-Chin Wang ,  Darrell M. Erb

发明人： Christy Mei-Chu Woo ,  Connie Pin-Chin Wang ,  Darrell M. Erb

IPC分类号： H01L21/3213 ,  H01L21/331 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： High reliable copper interconnects are formed with copper or a low resistivity copper alloy filling relatively narrow openings and partially filling relatively wider openings and a copper alloy having improved electromigration resistance selectively deposited in the relatively wider openings. The filled openings are recessed and a metal capping layer deposited followed by CMP. The metal capping layer prevents diffusion along the copper-capping layer interface while the copper alloy filling the relatively wider openings impedes electromigration along the grain boundaries.

摘要翻译： 通过铜或低电阻铜合金形成高可靠的铜互连，填充较窄的开口并部分地填充相对较宽的开口，并且具有改进的电迁移电阻的铜合金选择性地沉积在较宽的开口中。 填充的开口凹陷并且金属覆盖层沉积，然后沉积CMP。 金属覆盖层防止沿着铜覆盖层界面的扩散，而填充相对较宽的开口的铜合金阻止沿着晶界的电迁移。

公开(公告)号：US06454916B1

公开(公告)日：2002-09-24

申请号：US09477810

申请日：2000-01-05

申请人： Fei Wang ,  Steven C. Avanzino ,  Darrell M. Erb

发明人： Fei Wang ,  Steven C. Avanzino ,  Darrell M. Erb

IPC分类号： C25D1700

CPC分类号： C25D5/22 ,  B23H5/08 ,  C25D7/12 ,  C25D17/001

摘要： A deposition tool and a method for depositing a material within the recesses in a substrate of semiconductor wafer employs a rotatable diffuser that diffuses the plating material onto the top surface of a substrate. The diffuser is placed into contact with the semiconductor wafer and rotated while the plating material is applied through apertures in the diffuser. The plating material fills recesses patterned into the substrate of the semiconductor wafer but is prevented from forming to a significant degree on the top surface of the semiconductor wafer due to the contact and rotation of the diffuser. Since the plating material is not deposited on the top surface of the semiconductor wafer to any significant degree, chemical mechanical polishing (CMP) planarization is significantly reduced or completely eliminated.

摘要翻译： 沉积工具和用于在半导体晶片的衬底内的凹槽内沉积材料的方法采用将电镀材料扩散到衬底顶表面上的可旋转漫射器。 扩散器被放置成与半导体晶片接触并且当电镀材料通过扩散器中的孔施加时旋转。 电镀材料填充图案化到半导体晶片的衬底中的凹槽，但是由于扩散器的接触和旋转，防止了在半导体晶片的顶表面上形成很大程度。 由于电镀材料没有以任何显着的程度沉积在半导体晶片的顶表面上，所以化学机械抛光（CMP）平面化被显着地减少或完全消除。

公开(公告)号：US06169034A

公开(公告)日：2001-01-02

申请号：US09199352

申请日：1998-11-25

申请人： Steven C. Avanzino ,  Darrell M. Erb ,  Diana M. Schonauer ,  Kai Yang

发明人： Steven C. Avanzino ,  Darrell M. Erb ,  Diana M. Schonauer ,  Kai Yang

IPC分类号： H01L21461

CPC分类号： H01L21/3212 ,  C09G1/02 ,  C09K3/1463

摘要： Abrasion of Cu metallization during CMP is reduced and residual slurry particulate removal facilitated by employing a CMP slurry containing a dispersion of soft mineral particles having high solubility in dilute acids. Embodiments include CMP Cu metallization with a slurry containing magnesium oxide particles and removing any residual magnesium oxide particles after CMP with an organic acid, such as citric acid or acetic acid, or a dilute inorganic acid, such as hydrochloric, phosphoric, boric or fluoboric acid.

摘要翻译： 在CMP期间对Cu金属化的磨损降低，并且通过使用含有在稀酸中具有高溶解度的软矿物颗粒的分散体的CMP浆料来促进残留的浆料颗粒去除。 实施方案包括用含有氧化镁颗粒的浆料进行CMP Cu金属化，并在CMP之后用有机酸如柠檬酸或乙酸或稀无机酸如盐酸，磷酸，硼酸或氟硼酸除去残留的氧化镁颗粒 。

公开(公告)号：US6140239A

公开(公告)日：2000-10-31

申请号：US199266

申请日：1998-11-25

申请人： Steven C. Avanzino ,  Darrell M. Erb ,  Diana M. Schonauer ,  Kai Yang

发明人： Steven C. Avanzino ,  Darrell M. Erb ,  Diana M. Schonauer ,  Kai Yang

IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L21/321 ,  H01L21/304

CPC分类号： H01L21/02074 ,  H01L21/3212

摘要： Abrasion of Cu metallization during CMP is reduced and residual slurry particulate removal facilitated by employing a CMP slurry containing a dispersion of iron oxide particles having high solubility in dilute acids. Embodiments include CMP Cu metallization with a slurry containing iron oxide particles and removing residual iron oxide particles after CMP with an organic acid, such as oxalic acid or acetic acid, or a dilute inorganic acid, such as hydrochloric, boric or fluoroboric acid.

摘要翻译： 在CMP期间对Cu金属化的磨损减少，并且通过使用含有在稀酸中具有高溶解度的氧化铁颗粒的分散体的CMP浆料来促进残留的浆料颗粒去除。 实施方案包括用含有氧化铁颗粒的浆料和CMP之后用有机酸如草酸或乙酸除去残留的氧化铁颗粒，或稀释的无机酸如盐酸，硼酸或氟硼酸的CMP Cu金属化。

公开(公告)号：US06756306B2

公开(公告)日：2004-06-29

申请号：US10334387

申请日：2002-12-30

申请人： Steven C. Avanzino ,  Darrell M. Erb

发明人： Steven C. Avanzino ,  Darrell M. Erb

IPC分类号： H01L2144

CPC分类号： H01L21/02118 ,  H01L21/02167 ,  H01L21/02271 ,  H01L21/312 ,  H01L21/314 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834

摘要： The reliability and electromigration life-time of planarized metallization features, e.g., copper, inlaid in the surface of a layer of dielectric material, are enhanced by a chemical vapor deposition process for depositing a passivation layer over the metallization patterns which comprises maintaining on the upper surfaces of the metallization features, at or below a first temperature, an inhibiting film previously deposited thereon. The inhibiting film substantially inhibits oxide layer formation on the surface of the metallization features below the first temperature. Passivation layer deposition occurs at a second temperature higher than the first temperature such that the time interval between removal of the inhibiting film and formation of the passivation layer is short enough to substantially inhibit the formation of oxides on the surface of the metal feature.

摘要翻译： 通过用于在金属化图案上沉积钝化层的化学气相沉积工艺来增强镶嵌在介电材料层的表面中的平坦化金属化特征（例如铜）的可靠性和电迁移寿命，其包括保持在上部 处于或低于第一温度的金属化特征的表面是预先沉积在其上的抑制膜。 抑制膜基本上抑制在第一温度以下的金属化特征的表面上形成氧化物层。 钝化层沉积在高于第一温度的第二温度下发生，使得去除抑制膜和钝化层的形成之间的时间间隔足够短，从而基本上抑制金属特征表面上的氧化物的形成。

公开(公告)号：US06500754B1

公开(公告)日：2002-12-31

申请号：US09999661

申请日：2001-10-31

申请人： Darrell M. Erb ,  Steven C. Avanzino ,  Alline F. Myers

发明人： Darrell M. Erb ,  Steven C. Avanzino ,  Alline F. Myers

IPC分类号： H01L214763

CPC分类号： H01L21/76883

摘要： An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. Before planarization of the conductor core and the barrier layer, an anneal of the semiconductor substrate is performed at high temperatures of 400° C. and above to stimulate grain growth. After planarization, subsequent high temperature deposition of passivating or capping layers will not cause grain growth and hillocks will be suppressed.

摘要翻译： 因此，提供了具有半导体器件的半导体衬底的集成电路和制造方法。 在半导体基板上形成器件电介质层，在器件电介质层上形成的沟道电介质层形成有开口部。 阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。 在导体芯和阻挡层平坦化之前，在400℃及以上的高温下进行半导体衬底的退火以刺激晶粒生长。 在平坦化之后，随后的钝化层或覆盖层的高温沉积将不会导致晶粒生长并且抑制小丘。

公开(公告)号：US06319834B1

公开(公告)日：2001-11-20

申请号：US09639812

申请日：2000-08-17

申请人： Darrell M. Erb ,  Steven C. Avanzino ,  Fei Wang

发明人： Darrell M. Erb ,  Steven C. Avanzino ,  Fei Wang

IPC分类号： H01L2144

CPC分类号： H01L21/3212 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76879

摘要： A pattern of in-laid conductors is formed by a method utilizing electroplating and chemical-mechanical polishing (CMP). Embodiments include a first step of selectively filling recesses formed in the surface of a substrate with a metal by localized electroplating at a reduced thickness, planar-surfaced overburden or blanket layer thereon, and planarizing the surface by CMP utilizing a relatively soft CMP pad. Embodiments also include an apparatus comprising a porous pad applicator for selectively electroplating recesses formed in the surface of a workpiece.

摘要翻译： 通过使用电镀和化学机械抛光（CMP）的方法形成嵌入导体的图案。 实施例包括第一步骤，通过局部电镀在其上以薄的局部电镀，平面表面覆盖层或覆盖层选择性地填充形成在衬底的表面中的凹陷，并且通过使用相对较软的CMP衬垫的CMP来平坦化表面。 实施例还包括一种包括用于选择性地电镀在工件表面中形成的凹槽的多孔垫施加器的装置。