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1.发明申请公开(公告)号：US20070061671A1
公开(公告)日：2007-03-15
申请号：US11217081
申请日：2005-08-30
IPC分类号： H03M13/00
CPC分类号： G06F13/4243 , G06F11/1052
摘要： A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.
摘要翻译： 提出了一种使用数据协议将数据传输到数据存储器中的方法。 数据存储器是纠错码（ECC）存储器或非纠错码存储器。 数据协议具有不同的帧。 当数据被写入ECC存储器时，该协议包括数据屏蔽帧，其中数据屏蔽位被ECC位替换。 该方法被设计成使得可以使用相同的协议和至少相似的架构来建立ECC和非ECC DRAM。
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2.发明授权公开(公告)号：US07428689B2
公开(公告)日：2008-09-23
申请号：US11217081
申请日：2005-08-30
IPC分类号： G06F11/10
CPC分类号： G06F13/4243 , G06F11/1052
摘要： A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.
摘要翻译： 提出了一种使用数据协议将数据传输到数据存储器中的方法。 数据存储器是纠错码（ECC）存储器或非纠错码存储器。 数据协议具有不同的帧。 当数据被写入ECC存储器时，该协议包括数据屏蔽帧，其中数据屏蔽位被ECC位替换。 该方法被设计成使得可以使用相同的协议和至少相似的架构来建立ECC和非ECC DRAM。
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3.发明授权Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals 有权具有时钟信号再生电路的存储器模块和用于临时存储输入命令和地址信号的寄存器电路公开(公告)号：US07334150B2
公开(公告)日：2008-02-19
申请号：US11002148
申请日：2004-12-03
申请人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G06F1/04
摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.
摘要翻译： 半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。 时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。 时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供 对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。
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4.发明申请SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR THE TRANSFER OF WRITE AND READ DATA SIGNALS IN A SEMICONDUCTOR MEMORY SYSTEM 有权用于半导体存储器系统中写入和读取数据信号的半导体存储器系统和方法公开(公告)号：US20060104132A1
公开(公告)日：2006-05-18
申请号：US10986767
申请日：2004-11-15
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1018
摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.
摘要翻译： 用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串 具体的突发长度。 该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。
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公开(公告)号：US07173877B2
公开(公告)日：2007-02-06
申请号：US10955177
申请日：2004-09-30
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.
摘要翻译： 本发明涉及一种具有两条时钟线的存储器件的存储器系统。 本发明的一个实施例提供了一种存储器系统，其包括至少一个存储器件，用于控制存储器件的操作的存储器控制器，从存储器控制器的写时钟输出延伸到存储器的时钟端口的第一时钟线 向存储器件提供时钟信号的第二时钟线，以及从存储器件的时钟端口延伸到存储器控制器的读时钟输入端的第二时钟线，以将施加到存储器件的时钟端口的时钟信号转发回 到存储器控制器的读时钟输入。 存储器件还可以包括同步电路，其适于从存储器控制器接收时钟信号，并提供与转发的时钟信号同步的输出数据。
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6.发明授权Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system 有权半导体存储器系统和用于在半导体存储器系统中传送写和读数据信号的方法公开(公告)号：US07050340B1
公开(公告)日：2006-05-23
申请号：US10986767
申请日：2004-11-15
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1018
摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.
摘要翻译： 用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串 具体的突发长度。 该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。
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7.发明授权Memory device, memory controller and memory system having bidirectional clock lines 有权存储器件，存储器控制器和具有双向时钟线的存储器系统公开(公告)号：US07180821B2
公开(公告)日：2007-02-20
申请号：US10954869
申请日：2004-09-30
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C5/04 , G11C7/22 , G11C7/225
摘要： One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.
摘要翻译： 本发明的一个实施例提供了一种适于根据写时钟信号接收数据并根据读时钟信号输出数据的存储器件，包括配置成输出读时钟信号并接收写时钟信号的时钟端口 以及串行双向驱动器，被配置为经由时钟端口输出读取时钟信号，并经由时钟端口同时接收写时钟信号。
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公开(公告)号：US20060112230A1
公开(公告)日：2006-05-25
申请号：US10996956
申请日：2004-11-24
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： The present invention relates to an integrated memory device including: memory cells arranged at wordlines and bitlines, wherein the memory cells are addressable in sets of 2n bit, wherein n is an integer, a pre-fetch read unit to pre-fetch an addressed set of 2n data bit in parallel from the addressed memory area, buffer memory to buffer the number of pre-fetched data bits; a number m of output ports to output the data bits buffered in the buffer memory; an output controller for controlling the outputting of the data bits buffered in the buffer memory to the number m of output ports in groups of m bits in one or a plurality of successive cycles, characterized in that the number m of output ports is different to any of the possible numbers 2n of the sets of addressable memory cells.
摘要翻译： 本发明涉及一种集成存储器件，其包括：以字线和位线布置的存储器单元，其中存储器单元可以以2位为单位的集合寻址，其中n是整数，预取读取 单元，用于从寻址的存储器区域缓冲存储器并行地预取寻址的2 数据位组，以缓冲预取数据位的数量; 多个输出端口输出缓冲存储器中缓冲的数据位; 输出控制器，用于在一个或多个连续循环中控制以缓冲存储器缓冲的数据位输出到m位组的输出端口的数量m，其特征在于，输出端口的数量m不同于任何 的可寻址存储器单元组的可能数字2 。
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9.发明申请Memory device, memory controller and memory system having bidirectional clock lines 有权具有双向时钟线的存储器件，存储器控制器和存储器系统公开(公告)号：US20060067156A1
公开(公告)日：2006-03-30
申请号：US10954869
申请日：2004-09-30
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C5/04 , G11C7/22 , G11C7/225
摘要： One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.
摘要翻译： 本发明的一个实施例提供了一种适于根据写时钟信号接收数据并根据读时钟信号输出数据的存储器件，包括配置成输出读时钟信号并接收写时钟信号的时钟端口 以及串行双向驱动器，被配置为经由时钟端口输出读取时钟信号，并经由时钟端口同时接收写时钟信号。
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公开(公告)号：US20060123265A1
公开(公告)日：2006-06-08
申请号：US11002148
申请日：2004-12-03
申请人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Abdallah Bacha , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G06F1/04
摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.
摘要翻译： 半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。 时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。 时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供 对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。
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