公开(公告)号：US5989979A

公开(公告)日：1999-11-23

申请号：US208920

申请日：1998-12-10

申请人： Wen Jun Liu ,  Pei Ching Lee ,  Mei Sheng Zhou

发明人： Wen Jun Liu ,  Pei Ching Lee ,  Mei Sheng Zhou

IPC分类号： H01L21/311 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/31116 ,  H01L21/76202

摘要： A novel anisotropic plasma etching process for forming patterned silicon nitride (Si.sub.3 N.sub.4) layers with improved critical dimension (CD) control while minimizing the Si.sub.3 N.sub.4 footing at the bottom edge of the Si.sub.3 N.sub.4 pattern is achieved. A pad oxide/silicon nitride layer is deposited on a silicon substrate. A patterned photoresist layer is used as an etching mask for etching the silicon nitride layer. By this invention, a chlorine (Cl.sub.2) breakthrough plasma pre-etch forms a protective polymer layer on the sidewalls of the patterned photoresist and removes residue in the open areas prior to etching the Si.sub.3 N.sub.4. The Si.sub.3 N.sub.4 is then aniso-tropically plasma etched using an etch gas containing SF.sub.6. The polymer layer, formed during the Cl.sub.2 pre-etch, reduces the lateral recessing of the photoresist when the Si.sub.3 N.sub.4 is etched, and results in improved patterned Si.sub.3 N.sub.4 profiles with reduced CD bias, and minimizes Si.sub.3 N.sub.4 footings at the bottom edge of the Si.sub.3 N.sub.4 pattern.

摘要翻译： 实现了一种新颖的各向异性等离子体蚀刻工艺，用于在Si 3 N 4图案的底部边缘处最小化Si 3 N 4基脚的同时，形成具有改进的临界尺寸（CD）控制的图案化氮化硅（Si 3 N 4）层。 衬垫氧化物/氮化硅层沉积在硅衬底上。 使用图案化的光致抗蚀剂层作为用于蚀刻氮化硅层的蚀刻掩模。 通过本发明，氯（Cl2）穿透等离子体预蚀刻在图案化光致抗蚀剂的侧壁上形成保护性聚合物层，并且在蚀刻Si 3 N 4之前去除开放区域中的残余物。 然后使用含有SF6的蚀刻气体对Si 3 N 4进行各向异性等离子体蚀刻。 在Cl2预蚀刻期间形成的聚合物层在蚀刻Si 3 N 4时减少了光致抗蚀剂的侧向凹陷，并且导致改善的图案化Si3N4分布，具有降低的CD偏压，并且使Si 3 N 4图案的底部边缘处的Si 3 N 4基底最小化。

公开(公告)号：US06461969B1

公开(公告)日：2002-10-08

申请号：US09442314

申请日：1999-11-22

申请人： Pei Ching Lee ,  Wen Jun Liu ,  Mei Sheng Zhou

发明人： Pei Ching Lee ,  Wen Jun Liu ,  Mei Sheng Zhou

IPC分类号： H01L21302

CPC分类号： H01L21/31116

摘要： A method for dry plasma selective etching of a pattern in a silicon nitride dielectric layer formed over a semiconductor substrate employed within a microelectronics fabrication. There is provided a semiconductor substrate having formed thereupon a pad oxide layer over which is formed a silicon nitride dielectric layer. There is formed over the substrate a patterned photoresist etch mask layer. There is then selectively etched the pattern of the photoresist etch mask layer into the silicon nitride layer employing a four-step etching process with three plasma etching environments which include; (1) a “break-through” etching step; (2) a “bulk” etching step to remove a majority of the silicon nitride layer and a “buffer” etching step to remove the remainder of the silicon nitride layer; and (3) an “over-etch” step to complete removal of silicon nitride without excessive etching of underlying material. These steps comprise the selective etching of the patterned silicon nitride layer while maintaining control of critical dimensions, with attenuated microloading and over-etching of underlying material.

摘要翻译： 一种干法等离子体选择性蚀刻形成在微电子学制造中所采用的半导体衬底上的氮化硅介电层中的图案。 提供了在其上形成有氧化硅电介质层的衬垫氧化层形成的半导体衬底。 在衬底上形成图案化的光致抗蚀剂蚀刻掩模层。 然后使用具有三个等离子体蚀刻环境的四步蚀刻工艺将光致抗蚀剂蚀刻掩模层的图案选择性地蚀刻到氮化硅层中，其包括： （1）“突破”蚀刻步骤; （2）去除大部分氮化硅层的“本体”蚀刻步骤和“缓冲”蚀刻步骤以去除其余的氮化硅层; 和（3）“过蚀刻”步骤，以完全去除氮化硅而不过度蚀刻下面的材料。 这些步骤包括对图案化的氮化硅层的选择性蚀刻，同时保持关键尺寸的控制，具有减弱的微负载和对下面的材料的过蚀刻。

公开(公告)号：US06271115B1

公开(公告)日：2001-08-07

申请号：US09604065

申请日：2000-06-26

申请人： Wen Jun Liu ,  Simon Chooi ,  Mei Sheng Zhou ,  Raymond Joy

发明人： Wen Jun Liu ,  Simon Chooi ,  Mei Sheng Zhou ,  Raymond Joy

IPC分类号： H01L214763

CPC分类号： H01L21/02071

摘要： An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been developed. The method is a five step process, in which the first step is in a microwave generated plasma containing O2 and H2O; the second step is in a microwave generated plasma containing O2 and N2; the third step is in a microwave generated plasma containing H2O; the fourth step is in a microwave generated plasma containing O2 and N2; and the fifth step is in a microwave generated plasma containing H2O. The first step which initiates removal of photoresist while simultaneously beginning the passivation process causes residue-free removal of photoresist following etching of aluminum or aluminum-copper layers in chlorine bearing etchants.

摘要翻译： 已经开发了一种用于在含氯等离子体中蚀刻图案之后从蚀刻铝图案去除光致抗蚀剂掩模的改进方法。 该方法是五步法，其中第一步是在微波产生的含有O 2和H 2 O的等离子体中; 第二步是在微波产生的含有O2和N2的等离子体中; 第三步是在微波产生的含有H 2 O的等离子体中; 第四步是在微波产生的含有O2和N2的等离子体中; 并且第五步是在含有H 2 O的微波产生的等离子体中。 在同时开始钝化过程的同时开始除去光致抗蚀剂的第一步骤在蚀刻含氯蚀刻剂中的铝或铝 - 铜层之后会导致残留物去除光致抗蚀剂。

公开(公告)号：US08394724B2

公开(公告)日：2013-03-12

申请号：US11843629

申请日：2007-08-22

申请人： Hai Cong ,  Wei Loong Loh ,  Krishan Gopal ,  Xin Zhang ,  Mei Sheng Zhou ,  Pradeep Ramachandramurthy Yelehanka

发明人： Hai Cong ,  Wei Loong Loh ,  Krishan Gopal ,  Xin Zhang ,  Mei Sheng Zhou ,  Pradeep Ramachandramurthy Yelehanka

IPC分类号： H01L21/312

CPC分类号： H01L21/32137 ,  H01L21/32139

摘要： A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

摘要翻译： 用于形成具有减少的线端缩短（LES）的器件特征的方法包括修整器件特征以在蚀刻期间实现期望的子接地规则临界尺寸以形成器件特征。

公开(公告)号：US08324011B2

公开(公告)日：2012-12-04

申请号：US11853156

申请日：2007-09-11

申请人： Chyiu Hyia Poon ,  Alex See ,  Mei Sheng Zhou

发明人： Chyiu Hyia Poon ,  Alex See ,  Mei Sheng Zhou

IPC分类号： H01L21/00

CPC分类号： H01L21/324 ,  H01L21/268

摘要： The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.

摘要翻译： 本发明提供了一种通过向半导体结构施加温度相关的相位开关层来退火半导体的方法。 温度相关的相位开关层在预定温度下将相从非晶形变化为结晶。 当半导体结构退火时，电磁辐射在到达半导体结构之前通过温度相关的相位开关层。 当达到期望的退火温度时，温度相关的相位开关层基本上阻止电磁辐射到达半导体结构。 结果，半导体在晶片上以一致的温度退火。 温度相关的相位开关层改变相位的温度可以通过离子注入工艺来控制。

公开(公告)号：US20110281410A1

公开(公告)日：2011-11-17

申请号：US13190805

申请日：2011-07-26

申请人： JINPING LIU ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： JINPING LIU ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US08012839B2

公开(公告)日：2011-09-06

申请号：US12040562

申请日：2008-02-29

申请人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US07966142B2

公开(公告)日：2011-06-21

申请号：US12103690

申请日：2008-04-15

申请人： Wen Zhan Zhou ,  Zheng Zou ,  Jasper Goh ,  Mei Sheng Zhou

发明人： Wen Zhan Zhou ,  Zheng Zou ,  Jasper Goh ,  Mei Sheng Zhou

IPC分类号： G01D21/00 ,  G06F19/00

CPC分类号： H01L22/12 ,  G01B21/045 ,  G01B2210/56 ,  H01L22/20

摘要： A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (R2 value) represents the accuracy index of the MTUT.

摘要翻译： 描述了一种评估测量工具精度的方法。 多变量回归用于定义计量工具的准确性，以便考虑不同测量参数之间的相互作用。 被测量的测量工具（MTUT）和参考计量工具（RMT）用于测量一组测试曲线。 MTUT测量测试配置文件，以生成第一个测量参数的MTUT数据集。 RMT测量测试配置文件以生成用于第一测量参数的RMT数据集和至少第二测量参数。 然后执行多变量回归以为数据集生成最佳拟合平面。 测定系数（R2值）表示MTUT的精度指标。

公开(公告)号：US07776699B2

公开(公告)日：2010-08-17

申请号：US12025788

申请日：2008-02-05

申请人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L29/778

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636

摘要： A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.

摘要翻译： 一种晶体管器件结构，包括：由第一材料形成的衬底部分; 以及源区域，漏极区域和形成在所述衬底中的沟道区域，所述源极和漏极区域包括与所述第一材料不同的多个第二材料岛，所述岛被布置成在所述沟道区域中引起应变 底物。

公开(公告)号：US20090218597A1

公开(公告)日：2009-09-03

申请号：US12040562

申请日：2008-02-29

申请人： Jinping Liu ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。