公开(公告)号：US5989979A

公开(公告)日：1999-11-23

申请号：US208920

申请日：1998-12-10

申请人： Wen Jun Liu ,  Pei Ching Lee ,  Mei Sheng Zhou

发明人： Wen Jun Liu ,  Pei Ching Lee ,  Mei Sheng Zhou

IPC分类号： H01L21/311 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/31116 ,  H01L21/76202

摘要： A novel anisotropic plasma etching process for forming patterned silicon nitride (Si.sub.3 N.sub.4) layers with improved critical dimension (CD) control while minimizing the Si.sub.3 N.sub.4 footing at the bottom edge of the Si.sub.3 N.sub.4 pattern is achieved. A pad oxide/silicon nitride layer is deposited on a silicon substrate. A patterned photoresist layer is used as an etching mask for etching the silicon nitride layer. By this invention, a chlorine (Cl.sub.2) breakthrough plasma pre-etch forms a protective polymer layer on the sidewalls of the patterned photoresist and removes residue in the open areas prior to etching the Si.sub.3 N.sub.4. The Si.sub.3 N.sub.4 is then aniso-tropically plasma etched using an etch gas containing SF.sub.6. The polymer layer, formed during the Cl.sub.2 pre-etch, reduces the lateral recessing of the photoresist when the Si.sub.3 N.sub.4 is etched, and results in improved patterned Si.sub.3 N.sub.4 profiles with reduced CD bias, and minimizes Si.sub.3 N.sub.4 footings at the bottom edge of the Si.sub.3 N.sub.4 pattern.

摘要翻译： 实现了一种新颖的各向异性等离子体蚀刻工艺，用于在Si 3 N 4图案的底部边缘处最小化Si 3 N 4基脚的同时，形成具有改进的临界尺寸（CD）控制的图案化氮化硅（Si 3 N 4）层。 衬垫氧化物/氮化硅层沉积在硅衬底上。 使用图案化的光致抗蚀剂层作为用于蚀刻氮化硅层的蚀刻掩模。 通过本发明，氯（Cl2）穿透等离子体预蚀刻在图案化光致抗蚀剂的侧壁上形成保护性聚合物层，并且在蚀刻Si 3 N 4之前去除开放区域中的残余物。 然后使用含有SF6的蚀刻气体对Si 3 N 4进行各向异性等离子体蚀刻。 在Cl2预蚀刻期间形成的聚合物层在蚀刻Si 3 N 4时减少了光致抗蚀剂的侧向凹陷，并且导致改善的图案化Si3N4分布，具有降低的CD偏压，并且使Si 3 N 4图案的底部边缘处的Si 3 N 4基底最小化。

公开(公告)号：US6165871A

公开(公告)日：2000-12-26

申请号：US356003

申请日：1999-07-16

申请人： Eng Hua Lim ,  Chong Wee Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Pei Ching Lee

发明人： Eng Hua Lim ,  Chong Wee Lim ,  Soh Yun Siah ,  Kong Hean Lee ,  Pei Ching Lee

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L29/665 ,  H01L21/76232 ,  H01L21/823481

摘要： A method for forming a stepped shallow trench isolation is described. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the pad oxide layer. The first nitride layer is etched through where it is not covered by a mask to provide an opening to the pad oxide layer. A first trench is etched through the pad oxide layer within the opening and into the semiconductor substrate. A second nitride layer is deposited overlying the first nitride layer and filling the first trench. Simultaneously, the second nitride layer is anisotropically etched to form nitride spacers on the sidewalls of the first trench and the semiconductor substrate is etched into where it is not covered by the spacers to form a second trench. Ions are implanted into the semiconductor substrate underlying the second trench. The first and second trenches are filled with an oxide layer. Thereafter, the first nitride and pad oxide layers are removed completing the formation of shallow trench isolation in the fabrication of an integrated circuit device. This nitride spacer STI architecture prevents STI corner oxide recess and enables borderless contact formation. This unique process reduces junction leakage and also reduces contact leakage.

摘要翻译： 描述了形成阶梯式浅沟槽隔离的方法。 衬垫氧化物层沉积在半导体衬底的表面上。 沉积在衬垫氧化物层上的第一氮化物层。 蚀刻第一氮化物层，其中未被掩模覆盖，以提供衬垫氧化物层的开口。 通过开口内的衬垫氧化物层蚀刻第一沟槽并进入半导体衬底。 沉积第二氮化物层，覆盖第一氮化物层并填充第一沟槽。 同时，第二氮化物层被各向异性蚀刻以在第一沟槽的侧壁上形成氮化物间隔物，并且半导体衬底被蚀刻到不被间隔物覆盖的区域中以形成第二沟槽。 离子被注入到第二沟槽下面的半导体衬底中。 第一和第二沟槽填充有氧化物层。 此后，去除在制造集成电路器件时完成形成浅沟槽隔离的第一氮化物层和衬垫氧化物层。 该氮化物间隔物STI结构防止了STI拐角氧化物凹陷并且实现无边界接触形成。 这种独特的工艺可减少结漏电流并减少接触泄漏。

公开(公告)号：US07041591B1

公开(公告)日：2006-05-09

申请号：US11025034

申请日：2004-12-30

申请人： Pei-Ching Lee ,  Xian-Zhang Wang ,  E-Tung Chu

发明人： Pei-Ching Lee ,  Xian-Zhang Wang ,  E-Tung Chu

IPC分类号： H01L21/44 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  C25D5/02

CPC分类号： H05K3/242 ,  C25D5/022 ,  C25D7/12 ,  H01L21/4846 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/06 ,  H05K3/184 ,  H05K3/243 ,  H05K2203/175 ,  Y10S205/92 ,  H01L2224/0401

摘要： A method for fabricating a semiconductor package substrate having a plated metal layer on a conductive pad is proposed. First of all, a first resist layer is formed on a semiconductor package substrate having a plurality of traces and conductive pads on a surface thereof. The first resist layer is provided with at least an opening, such that the opening is able to contact the adjacent trace. Subsequently, a conductive film is formed in the opening, such that the conductive film can electrically connect the adjacent trace and conductive pad. After removing the first resist layer, a second resist layer having a plurality of openings is formed on the surface of the substrate to expose the conductive pad. Afterwards, an electroplating process is performed on the substrate, so that a metal layer is formed on an exposed surface of the conductive pad. The second resist layer and the conductive film are then removed from the substrate. A solder mask layer having a plurality of openings is also formed on the surface of the substrate to expose the conductive pad which has been covered by the metal layer using the electroplating process.

摘要翻译： 提出了一种在导电焊盘上制造具有电镀金属层的半导体封装基板的方法。 首先，在其表面上具有多个迹线和导电焊盘的半导体封装基板上形成第一抗蚀剂层。 第一抗蚀剂层设置有至少一个开口，使得开口能够接触相邻的迹线。 随后，在开口中形成导电膜，使得导电膜可以电连接相邻的迹线和导电焊盘。 在去除第一抗蚀剂层之后，在衬底的表面上形成具有多个开口的第二抗蚀剂层，以露出导电焊盘。 之后，在基板上进行电镀工序，在导电焊盘的露出面上形成金属层。 然后将第二抗蚀剂层和导电膜从基材上除去。 在基板的表面上还形成有多个开口的焊接掩模层，以便利用电镀工艺露出被金属层覆盖的导电焊盘。

公开(公告)号：US06461969B1

公开(公告)日：2002-10-08

申请号：US09442314

申请日：1999-11-22

申请人： Pei Ching Lee ,  Wen Jun Liu ,  Mei Sheng Zhou

发明人： Pei Ching Lee ,  Wen Jun Liu ,  Mei Sheng Zhou

IPC分类号： H01L21302

CPC分类号： H01L21/31116

摘要： A method for dry plasma selective etching of a pattern in a silicon nitride dielectric layer formed over a semiconductor substrate employed within a microelectronics fabrication. There is provided a semiconductor substrate having formed thereupon a pad oxide layer over which is formed a silicon nitride dielectric layer. There is formed over the substrate a patterned photoresist etch mask layer. There is then selectively etched the pattern of the photoresist etch mask layer into the silicon nitride layer employing a four-step etching process with three plasma etching environments which include; (1) a “break-through” etching step; (2) a “bulk” etching step to remove a majority of the silicon nitride layer and a “buffer” etching step to remove the remainder of the silicon nitride layer; and (3) an “over-etch” step to complete removal of silicon nitride without excessive etching of underlying material. These steps comprise the selective etching of the patterned silicon nitride layer while maintaining control of critical dimensions, with attenuated microloading and over-etching of underlying material.

摘要翻译： 一种干法等离子体选择性蚀刻形成在微电子学制造中所采用的半导体衬底上的氮化硅介电层中的图案。 提供了在其上形成有氧化硅电介质层的衬垫氧化层形成的半导体衬底。 在衬底上形成图案化的光致抗蚀剂蚀刻掩模层。 然后使用具有三个等离子体蚀刻环境的四步蚀刻工艺将光致抗蚀剂蚀刻掩模层的图案选择性地蚀刻到氮化硅层中，其包括： （1）“突破”蚀刻步骤; （2）去除大部分氮化硅层的“本体”蚀刻步骤和“缓冲”蚀刻步骤以去除其余的氮化硅层; 和（3）“过蚀刻”步骤，以完全去除氮化硅而不过度蚀刻下面的材料。 这些步骤包括对图案化的氮化硅层的选择性蚀刻，同时保持关键尺寸的控制，具有减弱的微负载和对下面的材料的过蚀刻。

公开(公告)号：US06277683B1

公开(公告)日：2001-08-21

申请号：US09514900

申请日：2000-02-28

申请人： Yelehanka Ramachandramurthy Pradeep ,  Henry Gerung ,  Jie Yu ,  Pei Ching Lee

发明人： Yelehanka Ramachandramurthy Pradeep ,  Henry Gerung ,  Jie Yu ,  Pei Ching Lee

IPC分类号： H01L218238

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665

摘要： A process for forming salicided CMOS devices, and non-salicide CMOS devices, on the same semiconductor substrate, using only one silicon nitride layer to provide a component for a composite spacer on the sides of the salicided CMOS devices, and to provide a blocking shape during metal silicide formation, for the non-salicided CMOS devices, has been developed. The process features the use of a disposable organic spacer, on the sides of polysilicon gate structures, used to define the heavily doped source/drain regions, for all CMOS devices. A silicon nitride layer, obtained via LPCVD procedures, at a temperature between 800 to 900° C., is then deposited and patterned to provide the needed spacer, on the sides of the CMOS devices experiencing the salicide process, while the same silicon nitride layer is used to provide the blocking shape needed to prevent metal suicide formation for the non-salicided CMOS devices.

摘要翻译： 在相同的半导体衬底上形成水化CMOS器件和非硅化物半导体器件的方法，其仅使用一个氮化硅层来提供用于复合间隔物的部件用于在水化CMOS器件的侧面，并提供阻挡形状 在金属硅化物形成期间，对于非水银CMOS器件，已经开发出来。 该方法的特征在于，对于所有CMOS器件，在多晶硅栅极结构的侧面上使用用于限定重掺杂源极/漏极区域的一次性有机间隔物。 然后在800至900℃的温度下通过LPCVD方法获得的氮化硅层被沉积和图案化以在经历自对准硅化物工艺的CMOS器件的侧面上提供所需的间隔物，而同一氮化硅层 用于提供防止非水银CMOS器件形成金属硅化所需的阻挡形状。