公开(公告)号：US08329541B2

公开(公告)日：2012-12-11

申请号：US12139010

申请日：2008-06-13

申请人： Peide Ye ,  Zhiyuan Cheng ,  Yi Xuan ,  Yanqing Wu ,  Bunmi Adekore ,  James Fiorenza

发明人： Peide Ye ,  Zhiyuan Cheng ,  Yi Xuan ,  Yanqing Wu ,  Bunmi Adekore ,  James Fiorenza

IPC分类号： H01L21/336

CPC分类号： H01L29/66522 ,  H01L21/02299 ,  H01L21/02301 ,  H01L21/02392 ,  H01L21/28264 ,  H01L29/517 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/778

摘要： Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

摘要翻译： 形成包括基于InP的材料的结构的方法，例如用作反型的晶体管，增强型器件。 可以通过ALD在包括In和P的半导体层上沉积电介质层。沟道层可以形成在具有类似于InP的晶格常数的晶格常数的缓冲层之上，缓冲层形成在具有晶格的衬底上 常数与InP的晶格常数不同。

公开(公告)号：US20090042344A1

公开(公告)日：2009-02-12

申请号：US12139010

申请日：2008-06-13

申请人： Peide Ye ,  Zhiyuan Cheng ,  Yi Xuan ,  Yanqing Wu ,  Bunmi Adekore ,  James Fiorenza

发明人： Peide Ye ,  Zhiyuan Cheng ,  Yi Xuan ,  Yanqing Wu ,  Bunmi Adekore ,  James Fiorenza

IPC分类号： H01L21/335 ,  H01L21/336

CPC分类号： H01L29/66522 ,  H01L21/02299 ,  H01L21/02301 ,  H01L21/02392 ,  H01L21/28264 ,  H01L29/517 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/778

摘要： Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

摘要翻译： 形成包括基于InP的材料的结构的方法，例如用作反型的晶体管，增强型器件。 可以通过ALD在包括In和P的半导体层上沉积电介质层。沟道层可以形成在具有类似于InP的晶格常数的晶格常数的缓冲层之上，缓冲层形成在具有晶格的衬底上 常数与InP的晶格常数不同。

公开(公告)号：US11605721B2

公开(公告)日：2023-03-14

申请号：US17006874

申请日：2020-08-30

申请人： Kaixuan Shi ,  Haodian Shi ,  Yanqing Wu ,  Anping Hu ,  Xibei Yu

发明人： Kaixuan Shi ,  Haodian Shi ,  Yanqing Wu ,  Anping Hu ,  Xibei Yu

IPC分类号： H01L29/45 ,  H01L21/443 ,  H01L29/22 ,  H01L29/93 ,  C23C14/35 ,  C23C14/18 ,  C22C21/00 ,  H01C7/00 ,  C22C19/05 ,  C22C14/00

摘要： An electrode with multiple metallic-layers structure formed by a magnetron sputtering technique for a semiconductor device and method for producing same is disclosed. The ceramic device includes at least one from selected group consisting of ZnO-MOV (metal oxide varistors), BaTiO3-PTC (positive temperature coefficient) thermistors, Mn3O4-NTC (negative temperature coefficient) thermistors, and capacitors. The multiple metallic-layers include a sputtered buffer layer and a sputtered electrical contact layer. The buffer layer includes at least one alloy selected form group consisting of NiCr (Ni from 50-90 wt %), TiNi (Ti from 40-60 wt %), and AlNi (Al from 40-70 wt %) and the thickness of this layer is from greater than zero to less than 100 nm. The electrical contact layer includes at least one of Cu, Ag, Pt, Au, or combination. More specifically, the electrode includes one of NiCr/Cu system, NiCr/Ag system, NiCr/Cu/Ag system, TiNi/Cu/Ag system, or AlNi/Cu/Ag system. The thickness ratio of the electrical contact layer to the intermetallic barrier layer is from 1 to 4.

公开(公告)号：US20130234762A1

公开(公告)日：2013-09-12

申请号：US13418066

申请日：2012-03-12

申请人： Shu-Jen Han ,  Yu-Ming Lin ,  Yanqing Wu

发明人： Shu-Jen Han ,  Yu-Ming Lin ,  Yanqing Wu

IPC分类号： H03K3/00 ,  H01L29/775

CPC分类号： H01L29/42364 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/66431 ,  H01L29/7781 ,  H01L29/78684

摘要： A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.

摘要翻译： 电路包括包括栅极和石墨烯通道的负差分电阻（NDR）器件和调制栅极上的栅极电压的栅极电压源，使得通过石墨烯通道的电流呈现负的差分电阻。

公开(公告)号：US20120181510A1

公开(公告)日：2012-07-19

申请号：US13352737

申请日：2012-01-18

申请人： Phaedon Avouris ,  Yanqing Wu ,  Wenjuan Zhu

发明人： Phaedon Avouris ,  Yanqing Wu ,  Wenjuan Zhu

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L21/28 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L27/0688 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/78684

摘要： A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.

摘要翻译： 三维集成电路包括半导体器件，形成在半导体器件上的绝缘体，形成在绝缘体中的互连以及形成在绝缘体上的石墨烯器件。

公开(公告)号：US08593180B2

公开(公告)日：2013-11-26

申请号：US13418066

申请日：2012-03-12

申请人： Shu-Jen Han ,  Yu-Ming Lin ,  Yanqing Wu

发明人： Shu-Jen Han ,  Yu-Ming Lin ,  Yanqing Wu

IPC分类号： H03K19/02

CPC分类号： H01L29/42364 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/66431 ,  H01L29/7781 ,  H01L29/78684

摘要： A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.

摘要翻译： 电路包括包括栅极和石墨烯通道的负差分电阻（NDR）器件和调制栅极上的栅极电压的栅极电压源，使得通过石墨烯通道的电流呈现负的差分电阻。

公开(公告)号：US08901680B2

公开(公告)日：2014-12-02

申请号：US13445029

申请日：2012-04-12

申请人： Jin Cai ,  Yanqing Wu ,  Wenjuan Zhu

发明人： Jin Cai ,  Yanqing Wu ,  Wenjuan Zhu

IPC分类号： H01L29/06

CPC分类号： H01L29/1606 ,  G01L9/0042 ,  G01L9/0051 ,  H01L27/0802 ,  H01L29/0649

摘要： Semiconductor nano pressure sensor devices having graphene membrane suspended over cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.

摘要翻译： 半导体纳米压力传感器装置具有悬浮在形成于半导体衬底中的空腔上的石墨烯膜。 悬浮的石墨烯膜用作用于感测压力（其可以制成非常薄）从约一个原子层到约10个原子层的活性电子机械膜，以提高半导体压力传感器装置的灵敏度和可靠性。

公开(公告)号：US08748871B2

公开(公告)日：2014-06-10

申请号：US13352737

申请日：2012-01-18

申请人： Phaedon Avouris ,  Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu ,  Yanqing Wu ,  Wenjuan Zhu

发明人： Phaedon Avouris ,  Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu ,  Yanqing Wu ,  Wenjuan Zhu

IPC分类号： H01L27/088

CPC分类号： H01L27/0688 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/78684

摘要： A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.

摘要翻译： 三维集成电路包括半导体器件，形成在半导体器件上的绝缘体，形成在绝缘体中的互连以及形成在绝缘体上的石墨烯器件。

公开(公告)号：US20220069099A1

公开(公告)日：2022-03-03

申请号：US17006874

申请日：2020-08-30

申请人： Kaixuan Shi ,  Haodian Shi ,  Yanqing Wu ,  Anping Hu ,  Xibei Yu

发明人： Kaixuan Shi ,  Haodian Shi ,  Yanqing Wu ,  Anping Hu ,  Xibei Yu

IPC分类号： H01L29/45 ,  H01L21/443 ,  H01L29/22 ,  H01L29/93 ,  C23C14/18 ,  C23C14/35

摘要： An electrode with multiple metallic-layers structure formed by a magnetron sputtering technique for a semiconductor device and method for producing same is disclosed. The ceramic device includes at least one from selected group consisting of ZnO-MOV (metal oxide varistors), BaTiO3-PTC (positive temperature coefficient) thermistors, Mn3O4-NTC (negative temperature coefficient) thermistors, and capacitors. The multiple metallic-layers include a sputtered buffer layer and a sputtered electrical contact layer. The buffer layer includes at least one alloy selected form group consisting of NiCr (Ni from 50-90 wt %), TiNi (Ti from 40-60 wt %), and AlNi (Al from 40-70 wt %) and the thickness of this layer is from greater than zero to less than 100 nm. The electrical contact layer includes at least one of Cu, Ag, Pt, Au, or combination. More specifically, the electrode includes one of NiCr/Cu system, NiCr/Ag system, NiCr/Cu/Ag system, TiNi/Cu/Ag system, or AlNi/Cu/Ag system. The thickness ratio of the electrical contact layer to the intermetallic barrier layer is from 1 to 4.

公开(公告)号：US08852985B2

公开(公告)日：2014-10-07

申请号：US13600469

申请日：2012-08-31

申请人： Jin Cai ,  Yanqing Wu ,  Wenjuan Zhu

发明人： Jin Cai ,  Yanqing Wu ,  Wenjuan Zhu

IPC分类号： H01L21/00 ,  H01L29/02

CPC分类号： H01L29/1606 ,  G01L9/0042 ,  G01L9/0051 ,  H01L27/0802 ,  H01L29/0649

摘要： Semiconductor nano pressure sensor devices having graphene membrane suspended over open cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.

摘要翻译： 半导体纳米压力传感器装置具有悬浮在半导体衬底中形成的开放空腔上的石墨烯膜。 悬浮的石墨烯膜用作用于感测压力（其可以制成非常薄）从约一个原子层到约10个原子层的活性电子机械膜，以提高半导体压力传感器装置的灵敏度和可靠性。