BIDIRECTIONAL COMMUNICATION PROTOCOL BETWEEN A SERIALIZER AND A DESERIALIZER
    1.
    发明申请
    BIDIRECTIONAL COMMUNICATION PROTOCOL BETWEEN A SERIALIZER AND A DESERIALIZER 有权
    一个串联和一个安抚者之间的双向通信协议

    公开(公告)号:US20080040765A1

    公开(公告)日:2008-02-14

    申请号:US11838064

    申请日:2007-08-13

    IPC分类号: H04N7/173

    CPC分类号: H04L5/16 H04L69/324

    摘要: A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

    摘要翻译: 一种方法提供用于第一设备和第二设备之间的数据通信的双向通信协议。 该方法包括:在第一时间间隔期间,将数据从第一设备发送到第二设备; 并且在第二时间间隔期间,(a)在发生第一事件之后,(i)暂停从第一设备到第二设备的数据传输; 和(ii)将控制数据从第二设备发送到第一设备; 和(b)在第二事件发生之后,将控制数据从第一设备发送到第二设备。

    SPREAD SPECTRUM CLOCK GENERATOR AND METHOD
    2.
    发明申请
    SPREAD SPECTRUM CLOCK GENERATOR AND METHOD 有权
    传播频谱发生器和方法

    公开(公告)号:US20080037613A1

    公开(公告)日:2008-02-14

    申请号:US11838084

    申请日:2007-08-13

    IPC分类号: H04B1/69

    CPC分类号: H04B15/04 H04B2215/067

    摘要: A spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which maintains a current state of the spread spectrum clock signal generator, receives as input value a next state of the spread spectrum clock signal generator and generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating a spread spectrum clock signal based on the clock phase selection signal.

    摘要翻译: 扩频时钟信号发生器和伴随方法提供了降低的电磁干扰的扩频时钟信号。 扩展频谱时钟信号发生器包括:(a)保持扩频时钟信号发生器的当前状态的状态机接收扩频时钟信号发生器的下一个状态作为输入值,并产生基于 当前和下一个州; (b)用于产生下一状态的随机数发生器; 和(c)用于基于时钟相位选择信号产生扩频时钟信号的波形发生电路。

    Bidirectional communication protocol between a serializer and a deserializer
    3.
    发明授权
    Bidirectional communication protocol between a serializer and a deserializer 有权
    串行器和解串器之间的双向通信协议

    公开(公告)号:US08332518B2

    公开(公告)日:2012-12-11

    申请号:US11838064

    申请日:2007-08-13

    IPC分类号: G06F15/16

    CPC分类号: H04L5/16 H04L69/324

    摘要: A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

    摘要翻译: 一种方法提供用于第一设备和第二设备之间的数据通信的双向通信协议。 该方法包括:在第一时间间隔期间,将数据从第一设备发送到第二设备; 并且在第二时间间隔期间,(a)在发生第一事件之后,(i)暂停从第一设备到第二设备的数据传输; 和(ii)将控制数据从第二设备发送到第一设备; 和(b)在第二事件发生之后,将控制数据从第一设备发送到第二设备。

    Spread spectrum clock generator and method
    4.
    发明授权
    Spread spectrum clock generator and method 有权
    扩频时钟发生器和方法

    公开(公告)号:US08565284B2

    公开(公告)日:2013-10-22

    申请号:US11838084

    申请日:2007-08-13

    IPC分类号: H04B1/00

    CPC分类号: H04B15/04 H04B2215/067

    摘要: A spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which maintains a current state of the spread spectrum clock signal generator, receives as input value a next state of the spread spectrum clock signal generator and generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating a spread spectrum clock signal based on the clock phase selection signal.

    摘要翻译: 扩频时钟信号发生器和伴随方法提供了降低的电磁干扰的扩频时钟信号。 扩展频谱时钟信号发生器包括:(a)保持扩频时钟信号发生器的当前状态的状态机接收扩频时钟信号发生器的下一个状态作为输入值,并产生基于 当前和下一个州; (b)用于产生下一状态的随机数发生器; 和(c)用于基于时钟相位选择信号产生扩频时钟信号的波形发生电路。

    LOW NOISE BIAS CIRCUIT FOR A PLL OSCILLATOR
    5.
    发明申请
    LOW NOISE BIAS CIRCUIT FOR A PLL OSCILLATOR 审中-公开
    用于PLL振荡器的低噪声偏置电路

    公开(公告)号:US20130076450A1

    公开(公告)日:2013-03-28

    申请号:US13244254

    申请日:2011-09-23

    IPC分类号: H03L7/08

    摘要: A system, method, and apparatus for generating a low noise bias current to improve jitter performance in a wide frequency range LC-based phase-locked loop (PLL) circuit for multi-speed clocking applications. A plurality of noise-reducing stages are coupled in series and disposed between a power supply and a voltage controlled oscillator (VCO) including: a first stage VCO regulator; and a second stage bias circuit having a plurality of PMOS transistors cascode-coupled to each other and optionally grouped into one or more parallel branches of cascode-coupled transistor pairs. Each branch can be automatically enabled by a calibration code based on the desired reference clock signal in order to provide a wide range of currents to the voltage controlled oscillator. The cascode coupled pair includes a bias transistor coupled in series with a self-biased current buffer to provide high output impedance with minimal current change for any input voltage change from noise.

    摘要翻译: 一种用于产生低噪声偏置电流以提高用于多速时钟应用的宽频率范围LC基锁相环(PLL)电路中的抖动性能的系统,方法和装置。 多个降噪级串联耦合并设置在电源和压控振荡器(VCO)之间,包括:第一级VCO调节器; 以及第二级偏置电路,其具有彼此串联耦合并可选地分组成共源共栅晶体管对的一个或多个并联支路的多个PMOS晶体管。 可以通过基于所需参考时钟信号的校准码来自动启用每个分支,以便向压控振荡器提供宽范围的电流。 共源共栅耦合对包括与自偏置电流缓冲器串联耦合的偏置晶体管,以便为噪声的任何输入电压变化提供最小电流变化的高输出阻抗。

    Low jitter large frequency tuning LC PLL for multi-speed clocking applications
    8.
    发明授权
    Low jitter large frequency tuning LC PLL for multi-speed clocking applications 有权
    低抖动大频率调谐LC PLL,用于多速时钟应用

    公开(公告)号:US08044724B2

    公开(公告)日:2011-10-25

    申请号:US12430430

    申请日:2009-04-27

    IPC分类号: H03L7/00

    摘要: The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

    摘要翻译: 本发明涉及用于生成用于多速时钟应用的低抖动大频率调谐基于LC的锁相环电路的系统和/或方法。 除了多个降噪功能之外,锁相环包括可实现宽环路带宽的可编程电荷泵和环路滤波器,能够实现宽VCO频率范围的可编程VCO和进一步实现宽范围的每通道时钟分频器 PLL频率范围。 此外,自动校准电路确保PLL中包含的VCO接收用于VCO频率范围内降噪的最佳电流。

    LOW JITTER LARGE FREQUENCY TUNING LC PLL FOR MULTI-SPEED CLOCKING APPLICATIONS
    9.
    发明申请
    LOW JITTER LARGE FREQUENCY TUNING LC PLL FOR MULTI-SPEED CLOCKING APPLICATIONS 有权
    低抖动大频率调谐LC PLL用于多速时钟应用

    公开(公告)号:US20100073051A1

    公开(公告)日:2010-03-25

    申请号:US12430430

    申请日:2009-04-27

    IPC分类号: H03L7/06

    摘要: ABSTRACT The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

    摘要翻译: 摘要本发明涉及用于生成用于多速时钟应用的低抖动大频率调谐基于LC的锁相环电路的系统和/或方法。 除了多个降噪功能之外,锁相环包括可实现宽环路带宽的可编程电荷泵和环路滤波器,能够实现宽VCO频率范围的可编程VCO和进一步实现宽范围的每通道时钟分频器 PLL频率范围。 此外,自动校准电路确保PLL中包含的VCO接收用于VCO频率范围内降噪的最佳电流。

    Method for enabling a photolab to process digital images and related data
    10.
    发明授权
    Method for enabling a photolab to process digital images and related data 有权
    使photolab能够处理数字图像和相关数据的方法

    公开(公告)号:US07126708B1

    公开(公告)日:2006-10-24

    申请号:US09945100

    申请日:2001-08-31

    IPC分类号: G06F15/00

    CPC分类号: G06Q30/00

    摘要: A system and business method for enabling photolabs to provide digital image processing services, and at the same time, to provide the photolabs with the ability to use their own branding in connection with their services and to the control of all business aspects of the service, including the creation of a customized website, digital image product offerings, branding, pricing, promotions, advertisements, and film prints and related image imprinted product fulfillment.

    摘要翻译: 一种用于使photolabs能够提供数字图像处理服务的系统和业务方法,同时,为了使photolabs能够使用自己的品牌与其服务相关联并控制服务的所有业务方面, 包括创建定制网站,数字图像产品,品牌,定价,促销,广告,电影和相关图像印刷产品的实现。