公开(公告)号：US08565284B2

公开(公告)日：2013-10-22

申请号：US11838084

申请日：2007-08-13

申请人： Paul D. Ta ,  Wei Wang ,  Alvin Wang ,  Peter D. Bradshaw

发明人： Paul D. Ta ,  Wei Wang ,  Alvin Wang ,  Peter D. Bradshaw

IPC分类号： H04B1/00

CPC分类号： H04B15/04 ,  H04B2215/067

摘要： A spread spectrum clock signal generator and an accompanying method provide a spread spectrum clock signal of a reduced electromagnetic interference. The spread spectrum clock signal generator includes (a) a state machine, which maintains a current state of the spread spectrum clock signal generator, receives as input value a next state of the spread spectrum clock signal generator and generates a clock phase selection signal based on the current and next states; (b) a random number generator for generating the next state; and (c) a waveform generation circuit for generating a spread spectrum clock signal based on the clock phase selection signal.

摘要翻译： 扩频时钟信号发生器和伴随方法提供了降低的电磁干扰的扩频时钟信号。 扩展频谱时钟信号发生器包括：（a）保持扩频时钟信号发生器的当前状态的状态机接收扩频时钟信号发生器的下一个状态作为输入值，并产生基于 当前和下一个州; （b）用于产生下一状态的随机数发生器; 和（c）用于基于时钟相位选择信号产生扩频时钟信号的波形发生电路。

公开(公告)号：US5134316A

公开(公告)日：1992-07-28

申请号：US626347

申请日：1990-12-12

申请人： Paul D. Ta

发明人： Paul D. Ta

IPC分类号： G11C7/10 ,  G11C8/06 ,  H03K19/0185

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/06 ,  H03K19/018521

摘要： A buffer with reduced output swing characterized by a CMOS logic level compatible input, an output adapted to develop a reduced voltage swing output signal, and a precharged converter circuit coupled between the output and the input for converting the input signal to the output signal. The precharged converter circuit includes a voltage range conversion stage coupling the input to the output of the buffer and a precharger stage coupled to the voltage range conversion stage to provide the voltage range conversion stage with a ready supply of charge to quickly change the output signal in response to a change in the input signal. A method for reducing output swing on a buffer includes precharging a voltage range conversion circuit capable of developing an output signal which is variable within an output range and coupling the conversion circuit to an input signal which is variable within an input range which is larger than the output range.

摘要翻译： 具有降低的输出摆​​幅的缓冲器，其特征在于CMOS逻辑电平兼容输入，适于产生降低的电压摆幅输出信号的输出，以及耦合在输出和输入之间的预充电转换器电路，用于将输入信号转换为输出信号。 预充电转换器电路包括将输入耦合到缓冲器的输出的电压范围转换级和耦合到电压范围转换级的预充电级，以提供电压范围转换级，以便快速地将输出信号改变 响应输入信号的变化。 一种用于减小缓冲器上的输出摆幅的方法，包括对能够产生在输出范围内可变的输出信号的电压范围转换电路进行预充电，并将转换电路耦合到输入信号，该输入信号在大于 输出范围。

公开(公告)号：US5515012A

公开(公告)日：1996-05-07

申请号：US442850

申请日：1995-05-17

申请人： Bharat Bhushan ,  Christopher G. Arcus ,  Paul D. Ta

发明人： Bharat Bhushan ,  Christopher G. Arcus ,  Paul D. Ta

IPC分类号： H03K3/0231 ,  H03K3/03 ,  H03L7/099 ,  H03B5/04

CPC分类号： H03L7/0995 ,  H03K3/0231 ,  H03K3/0322

摘要： A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.

摘要翻译： 锁相环电路的环形多级VCO包括两个或更多个差分放大器级。 锁相环包括连接在控制电压端子和电压 - 电流转换器级之间的低通滤波器，其包括具有源电阻器R1的第一源极跟随器MOS晶体管M1和连接到第二二极管连接的MOS晶体管M2 其漏极端子。 差分放大器级包括电流源MOS晶体管M10，其电流源MOS晶体管M10的栅极端子连接到第一MOS晶体管M1的漏极，以电流镜像M1的漏极电流。 差分放大器级还包括连接到电流源MOS晶体管M10的漏极端子的一对MOS晶体管M4和M5。 MOS晶体管M4的栅极端子为IN端子，MOS晶体管M5的栅极端子为IN端子。 MOS晶体管M4的漏极端子为差分放大器级提供OUT信号，MOS晶体管M5的漏极端为差分放大器级提供OUT信号。 MOS晶体管M6形成MOS晶体管M4的负载阻抗，MOS晶体管M7形成MOS晶体管M5的负载阻抗。 M6和M7的栅极端子连接到锁相环的电压控制输入端。

公开(公告)号：US08332518B2

公开(公告)日：2012-12-11

申请号：US11838064

申请日：2007-08-13

申请人： Peter D. Bradshaw ,  Wei Wang ,  Paul D. Ta ,  Bill R-S Tang ,  Alvin Wang

发明人： Peter D. Bradshaw ,  Wei Wang ,  Paul D. Ta ,  Bill R-S Tang ,  Alvin Wang

IPC分类号： G06F15/16

CPC分类号： H04L5/16 ,  H04L69/324

摘要： A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

摘要翻译： 一种方法提供用于第一设备和第二设备之间的数据通信的双向通信协议。 该方法包括：在第一时间间隔期间，将数据从第一设备发送到第二设备; 并且在第二时间间隔期间，（a）在发生第一事件之后，（i）暂停从第一设备到第二设备的数据传输; 和（ii）将控制数据从第二设备发送到第一设备; 和（b）在第二事件发生之后，将控制数据从第一设备发送到第二设备。

公开(公告)号：US20110299577A1

公开(公告)日：2011-12-08

申请号：US13211915

申请日：2011-08-17

申请人： Bill R-S Tang ,  Paul D. Ta

发明人： Bill R-S Tang ,  Paul D. Ta

IPC分类号： H04B1/38

CPC分类号： H04L25/0276 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45632 ,  H03F2203/45101 ,  H03F2203/45138 ,  H03F2203/45418 ,  H03F2203/45466 ,  H03F2203/45681

摘要： In a transceiver, a transmitter circuit is provided substantially the same common-mode voltage regardless of whether the transceiver is in a transmitting or receiving mode. In one embodiment, the transmitter circuit includes a driver circuit which, in the transmission mode of the transceiver, drives an output differential signal, and which, in the receiving mode of the transceiver, provides a termination circuit for an input differential signal. A variable resistor is provided to connect between a supply voltage and the driver circuit, the resistance of the variable resistor is selected such that the common-mode voltage of the output differential signal of the transmission mode substantially equals the common-mode voltage in the input differential signal of the receiving mode.

摘要翻译： 在收发器中，发射机电路提供基本上相同的共模电压，而不管收发器是处于发送还是接收模式。 在一个实施例中，发射机电路包括在收发器的传输模式下驱动输出差分信号的驱动器电路，以及在收发器的接收模式下，为输入差分信号提供终端电路。 提供可变电阻器以连接电源电压和驱动器电路之间，选择可变电阻器的电阻，使得传输模式的输出差分信号的共模电压基本上等于输入中的共模电压 接收模式的差分信号。

公开(公告)号：US08027377B2

公开(公告)日：2011-09-27

申请号：US11838069

申请日：2007-08-13

申请人： Bill R-S Tang ,  Paul D. Ta

发明人： Bill R-S Tang ,  Paul D. Ta

IPC分类号： H04B1/38

CPC分类号： H04L25/0276 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45632 ,  H03F2203/45101 ,  H03F2203/45138 ,  H03F2203/45418 ,  H03F2203/45466 ,  H03F2203/45681

摘要： In a transceiver, a transmitter circuit is provided substantially the same common-mode voltage regardless of whether the transceiver is in a transmitting or receiving mode. In one embodiment, the transmitter circuit includes a driver circuit which, in the transmission mode of the transceiver, drives an output differential signal, and which, in the receiving mode of the transceiver, provides a termination circuit for an input differential signal. A variable resistor is provided to connect between a supply voltage and the driver circuit, the resistance of the variable resistor is selected such that the common-mode voltage of the output differential signal of the transmission mode substantially equals the common-mode voltage in the input differential signal of the receiving mode.

摘要翻译： 在收发器中，发射机电路提供基本上相同的共模电压，而不管收发器是处于发送还是接收模式。 在一个实施例中，发射机电路包括在收发器的传输模式下驱动输出差分信号的驱动器电路，以及在收发器的接收模式下，为输入差分信号提供终端电路。 提供可变电阻器以连接电源电压和驱动器电路之间，选择可变电阻器的电阻，使得传输模式的输出差分信号的共模电压基本上等于输入中的共模电压 接收模式的差分信号。

公开(公告)号：US5227673A

公开(公告)日：1993-07-13

申请号：US612172

申请日：1990-11-13

申请人： Paul D. Ta

发明人： Paul D. Ta

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185

CPC分类号： H03K19/018521 ,  H03K19/0013 ,  H03K19/00361 ,  H03K19/01707 ,  H03K19/018514

摘要： A differential output buffer formed on a monolithic semiconductor substrate characterized by a bias generator coupled to a voltage source and a output stage coupled to the bias generator. The bias generator develops a bias output having a voltage level less than that of the voltage source. The output stage is responsive to a pair of complementary CMOS logic level inputs and uses the bias output of the bias generator to develop a pair of corresponding, low voltage swing outputs. In one embodiment the bias generator and the output stage operate in an open-loop and produce output signals which swing approximately two volts and in another embodiment the bias generator and the output stage operate in a closed-loop configuration and produce output signals which swing approximately one volt.

摘要翻译： 形成在单片半导体衬底上的差分输出缓冲器，其特征在于耦合到电压源的偏置发生器和耦合到所述偏置发生器的输出级。 偏置发生器产生具有小于电压源的电压电平的偏置输出。 输出级响应一对互补CMOS逻辑电平输入，并使用偏置发生器的偏置输出来开发一对相应的低电压摆幅输出。 在一个实施例中，偏置发生器和输出级在开环中工作并产生摆动大约两伏的输出信号，在另一个实施例中，偏置发生器和输出级以闭环配置工作并产生大约摆动的输出信号 一伏。

公开(公告)号：US5070307A

公开(公告)日：1991-12-03

申请号：US631620

申请日：1990-12-21

申请人： Paul D. Ta

发明人： Paul D. Ta

IPC分类号： H03F1/02

CPC分类号： H03F1/0261

摘要： A receiver is configured as a multistage differential amplifier. A front differential transconductance amplifier provides complementary outputs which respectively control current sources for an intermediate differential amplifier and a final differential amplifier. The output of the intermediate differential amplifier controls the mirror-current load of the final differential amplifier. The final current source and the final mirror-current load are controlled so that they induce a push-pull effect on the current output. When a high output is required, the output current is increased to charge the output capacitance more quickly. When a low output is required, the augmented current source drains the output capacitance more quickly. The net result is an enhanced slew rate for the receiver. The receiver can thus operate at higher frequencies and handle greater information rates.

摘要翻译： 接收机被配置为多级差分放大器。 前置差分跨导放大器提供互补输出，分别控制中间差分放大器和最终差分放大器的电流源。 中间差分放大器的输出控制最终差分放大器的镜面电流负载。 控制最终电流源和最终的镜面电流负载，使得它们对电流输出引起推挽效应。 当需要高输出时，输出电流增加以更快地对输出电容充电。 当需要低输出时，增大的电流源会更快地消耗输出电容。 最终的结果是接收机的压摆率提高。 因此，接收机可以在较高频率下操作并处理更大的信息速率。

公开(公告)号：US5523723A

公开(公告)日：1996-06-04

申请号：US443131

申请日：1995-05-17

申请人： Christopher G. Arcus ,  Bharat Bhushan ,  Paul D. Ta

发明人： Christopher G. Arcus ,  Bharat Bhushan ,  Paul D. Ta

IPC分类号： H03K3/0231 ,  H03K3/03 ,  H03L7/099 ,  H03B5/04

CPC分类号： H03L7/0995 ,  H03K3/0231 ,  H03K3/0322

摘要： A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the drain terminal of transistor M9.

摘要翻译： 锁相环电路的环形多级VCO包括两个或更多个差分放大器级。 锁相环包括连接在控制电压端子和电压 - 电流转换器级之间的低通滤波器，其包括具有源电阻器R1的第一源极跟随器MOS晶体管M1和与其连接的二极管连接的MOS晶体管M2 漏极端子。 电流源MOS晶体管M8具有连接到第一MOS晶体管M1的漏极的栅极端子，使得晶体管M8镜像晶体管M1的电流。 二极管连接的晶体管M9的栅极端子和其漏极端子连接在一起，并且还连接到晶体管M8的漏极端子。 差分放大器级包括电流源MOS晶体管M10，其电流源MOS晶体管M10的栅极端子连接到第一MOS晶体管M1的漏极，以电流镜像M1的漏极电流。 差分放大器级还包括连接到电流源MOS晶体管M10的漏极端子的一对MOS晶体管M4和M5。 MOS晶体管M4的栅极端子为IN端子，MOS晶体管M5的栅极端子为IN端子。 MOS晶体管M4的漏极端子为差分放大器级提供OUT信号，MOS晶体管M5的漏极端为差分放大器级提供OUT信号。 MOS晶体管M6形成MOS晶体管M4的负载阻抗，MOS晶体管M7形成MOS晶体管M5的负载阻抗。 M6和M7的栅极端子连接到晶体管M9的漏极端子。

公开(公告)号：US5495184A

公开(公告)日：1996-02-27

申请号：US371724

申请日：1995-01-12

申请人： Andre P. Des Rosiers ,  Paul D. Ta

发明人： Andre P. Des Rosiers ,  Paul D. Ta

IPC分类号： H03K19/00 ,  H03K19/0185

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： An output buffer contains a totem-pole structure of four CMOS transistors. The top two are PMOS devices and the bottom two are NMOS devices. The top and bottom transistors function as output current switches which alternatively turn on and off the current flow from either VSS or VDD to the resistive termination load Rt. The middle two devices are connected to DC voltage references which control a precise amounts of current sourced to a load using a precision current source and sunk from a load using and to a precision current sink. The reference voltages for the precision current source and the current sink uses a negative feedback circuit which is referenced to a resistor ladder and a current source controlled by a band-gap reference source. This allows for on-chip referencing of ECL levels and control of reference voltages and currents in spite of variation is process, voltage, and temperature. Internal ECL reference levels signals V.sub.OL and V.sub.OH are used to control the output levels. Operational amplifiers drive the respective transistors such that voltage at the drains of the current source and sink transistors equals the ECL reference inputs VOH and VOL. These control voltages generate a precise currents through a replica stage and are also applied to the output stage. All of the devices in the reference control circuit are scaled to reduce DC power dissipation. For differential operation, a second totem-pole driver circuit is used with the inverse input data signal for controlling the output current switches.

摘要翻译： 输出缓冲器包含四个CMOS晶体管的图腾柱结构。 前两者是PMOS器件，底部两个是NMOS器件。 顶部和底部晶体管用作输出电流开关，其交替地接通或断开从VSS或VDD到电阻终端负载Rt的电流。 中间两个装置连接到直流电压基准，其使用精密电流源控制来自负载的精确电流量，并且使用和使用精密电流吸收器从负载沉没。 精密电流源和电流吸收器的参考电压使用负反馈电路，参考电阻梯形电压和由带隙基准源控制的电流源。 这允许片上参考ECL电平和控制参考电压和电流，尽管变化是过程，电压和温度。 内部ECL参考电平信号VOL和VOH用于控制输出电平。 运算放大器驱动相应的晶体管，使得电流源极和漏极晶体管的漏极处的电压等于ECL参考输入VOH和VOL。 这些控制电压通过复制级产生精确的电流，并且也被施加到输出级。 参考控制电路中的所有器件都被缩放以降低直流功耗。 对于差分操作，使用第二图腾柱驱动电路与逆输入数据信号来控制输出电流开关。