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1.发明申请公开(公告)号：US20100061497A1
公开(公告)日：2010-03-11
申请号：US12547342
申请日：2009-08-25
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H04L7/00
CPC分类号： G06F13/4291 , H04L7/005 , H04L7/0083
摘要： A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
摘要翻译： 用于串行链路端口的接收器，其通过连接到转发的时钟信号通道的时钟数据恢复环路来增强。 接收机包括由相位位置逻辑控制的相位插值装置，它通过数字低通滤波器从时钟数据恢复环路的本地相位更新信号中获取其更新信号。 接收机还提供全局相位更新源选择逻辑，以控制哪个时钟数据恢复环路正在分发相位更新信息，哪个时钟数据恢复环路正在接收基于时钟分析块的相位更新信息。
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2.发明授权公开(公告)号：US08149979B2
公开(公告)日：2012-04-03
申请号：US12547342
申请日：2009-08-25
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H04L7/00
CPC分类号： G06F13/4291 , H04L7/005 , H04L7/0083
摘要： A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
摘要翻译： 用于串行链路端口的接收器，其通过连接到转发的时钟信号通道的时钟数据恢复环路来增强。 接收机包括由相位位置逻辑控制的相位插值装置，它通过数字低通滤波器从时钟数据恢复环路的本地相位更新信号中获取其更新信号。 接收机还提供全局相位更新源选择逻辑，以控制哪个时钟数据恢复环路正在分发相位更新信息，哪个时钟数据恢复环路正在接收基于时钟分析块的相位更新信息。
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3.发明授权Pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling devices and methods 失效具有双抽头加扰设备和方法的互连的伪随机比特序列（PRBS）同步公开(公告)号：US07492807B1
公开(公告)日：2009-02-17
申请号：US12098878
申请日：2008-04-07
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H04B1/00
CPC分类号： G06F13/4234
摘要： A method for synchronizing interconnects in a link system according to various embodiments can include receiving input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scrambling the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmitting the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler; synchronizing the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; using an edge detection or transition detection device for synchronization of the descrambler to the scrambler; and de-scrambling the transmitted scrambled data at the receive side resulting in the input data.
摘要翻译： 根据各种实施例的用于在链路系统中同步互连的方法可以包括在发送侧接收输入数据，所述发送侧包括至少一个伪随机比特序列加扰器; 经由具有双抽头序列的伪随机比特加扰器在发送侧加扰输入数据，导致加扰数据; 通过经由互连所述多个通道的总线将具有多个通道所有通道的双抽头序列的加扰数据发送到接收侧，所述接收侧包括至少一个伪随机位序列解扰器; 将所述至少一个伪随机比特序列加扰器同步至所述至少一个伪随机比特序列解扰器; 使用边缘检测或转换检测装置来将解扰器同步到扰频器; 并且在接收侧对发送的加扰数据进行去加扰，得到输入数据。
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公开(公告)号：US08645620B2
公开(公告)日：2014-02-04
申请号：US12143889
申请日：2008-06-23
IPC分类号： G06F12/00
CPC分类号： G06F12/02 , G06F12/0223 , G11C15/00
摘要： An interfacing apparatus and related method is provided for configuring to couple a plurality of memory devices being addressable by means of an address space to a processing unit. In one embodiment, the apparatus comprises a first memory access unit being adapted for receiving a memory address from said processing unit and for accessing said memory devices accordingly based on the address provided. It also comprises a second memory access unit being adapted for receiving content data from the processing unit and for controlling a search or update function accordingly for the received content data in one or more of the memory devices. In addition, an allocation unit is also provided for allocating a first part of the address space of the memory devices to said first memory access unit and allocating a second part of the address space of said memory devices to the second memory access unit, each of the memory access units being assigned to corresponding memory devices of the plurality of memory devices.
摘要翻译： 提供了一种接口装置和相关方法，用于将通过地址空间寻址的多个存储器件耦合到处理单元。 在一个实施例中，该装置包括第一存储器存取单元，其适于从所述处理单元接收存储器地址，并根据所提供的地址相应地访问所述存储器件。 它还包括第二存储器存取单元，其适于从处理单元接收内容数据，并用于相应地控制一个或多个存储器件中的所接收的内容数据的搜索或更新功能。 此外，还提供分配单元，用于将存储器件的地址空间的第一部分分配给所述第一存储器存取单元，并将所述存储器件的地址空间的第二部分分配给第二存储器存取单元， 所述存储器访问单元被分配给所述多个存储器件的相应的存储器件。
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5.发明授权公开(公告)号：US07684534B2
公开(公告)日：2010-03-23
申请号：US11484406
申请日：2006-07-11
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H03D3/24
CPC分类号： G06F13/4291 , H04L7/005 , H04L7/0083
摘要： A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
摘要翻译： 用于串行链路端口的接收器，其通过连接到转发的时钟信号通道的时钟数据恢复环路来增强。 接收机包括由相位位置逻辑控制的相位插值装置，它通过数字低通滤波器从时钟数据恢复环路的本地相位更新信号中获取其更新信号。 接收机还提供全局相位更新源选择逻辑，以控制哪个时钟数据恢复环路正在分发相位更新信息，哪个时钟数据恢复环路正在接收基于时钟分析块的相位更新信息。
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公开(公告)号：US20090006782A1
公开(公告)日：2009-01-01
申请号：US12143889
申请日：2008-06-23
IPC分类号： G06F12/00
CPC分类号： G06F12/02 , G06F12/0223 , G11C15/00
摘要： An apparatus and a corresponding method for coupling a memory device being addressable by means of an address space to a processing unit, the apparatus consisting: a first memory access unit being adapted for receiving a memory address from the processing unit and for accessing the memory device by the received memory address; a second memory access unit being adapted for receiving content data (an input key) from the processing unit and for controlling a search for the received content data in the memory device, and an allocation unit for allocating a first part of the address space of the memory device to the first memory access unit and a second part of the address space of the memory device to the second memory access unit. A storage medium to perform coupling a memory device being addressable by means of an address space to a processing unit is also provided.
摘要翻译： 一种用于将可通过地址空间寻址的存储器件耦合到处理单元的装置和相应方法，所述装置包括：第一存储器存取单元，适于从所述处理单元接收存储器地址并访问存储器件 由接收的存储器地址; 第二存储器存取单元，其适于从所述处理单元接收内容数据（输入密钥），并且用于控制对所述存储器件中的所接收的内容数据的搜索;以及分配单元，用于分配所述存储器存储单元的地址空间的第一部分 存储器设备到第一存储器存取单元以及存储器件的地址空间的第二部分到第二存储器存取单元。 还提供了一种用于通过地址空间将可寻址的存储器件耦合到处理单元的存储介质。
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7.发明申请PSEUDO-RANDOM BIT SEQUENCE (PRBS) SYNCHRONIZATION FOR INTERCONNECTS WITH DUAL-TAP SCRAMBLING DEVICES 审中-公开具有双TAP SCRAMBLING设备的互连的PSEUDO随机比特序列（PRBS）同步公开(公告)号：US20090252326A1
公开(公告)日：2009-10-08
申请号：US12325102
申请日：2008-11-28
申请人： Peter Buchmann , Martin Leo Schmatz
发明人： Peter Buchmann , Martin Leo Schmatz
IPC分类号： H04L9/22
CPC分类号： G06F13/4234
摘要： A system for synchronizing interconnects in a link system according to various embodiments can include a computer configured to receive input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scramble the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmit the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler, and the receive side directly connected to the transmit side via the bus; synchronize the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; and de-scramble the transmitted scrambled data at the receive side resulting in the input data.
摘要翻译： 根据各种实施例的用于在链路系统中同步互连的系统可以包括被配置为在发送侧接收输入数据的计算机，所述发送侧包括至少一个伪随机位序列加扰器; 通过具有双抽头序列的伪随机比特加扰器在发送侧加扰输入数据，导致加扰数据; 通过连接多个通道的总线将具有多个通道所有通道的双抽头序列的加扰数据发送到接收侧，接收侧包括至少一个伪随机比特序列解扰器，以及直接连接的接收侧 经由总线发送到发送侧; 将所述至少一个伪随机比特序列加扰器同步至所述至少一个伪随机比特序列解扰器; 并且在接收侧解密发送的加扰数据，从而产生输入数据。
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公开(公告)号：US07679459B2
公开(公告)日：2010-03-16
申请号：US11962681
申请日：2007-12-21
IPC分类号： H03B27/00
CPC分类号： H03L7/0995 , H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/06 , H04L7/033 , H04L7/0337
摘要： A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.
摘要翻译： 用于产生多相的信号发生器包括具有至少一个第一可调节延迟级的环形振荡器和串行布置的至少一个第二延迟级，其中第一延迟级的输出被提供用于传送至少一个第一输出相位和 提供第二延迟级的输出用于传递至少一个第二输出相位和用于调整第一可调延迟级的延迟的调整电路，其中调整电路用于调整第一输出相位与第一输出相位之间的相位关系 通过设置第一延迟级的第一传播延迟来实现第二输出相位。
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公开(公告)号：US07646839B2
公开(公告)日：2010-01-12
申请号：US11249851
申请日：2005-10-13
IPC分类号： H03D3/24
CPC分类号： H03L7/08 , H03L7/095 , H03L7/0995 , H03L7/10 , H04L7/0337 , H04L2027/0067
摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
摘要翻译： 描述了统一的单向串行链路，用于通过诸如芯片到芯片或卡到卡互连的有线介质提供数据。 它由一个传输部分和一个接收部分组成，它们被成对地运行以允许串行数据通信。 串行链路作为VLSI ASIC模块的一部分实现，并从主机模块中获得其功率，数据和时钟要求。 逻辑发送器部分包含锁相环（PLL），双位数据寄存器，有限脉冲响应（FIR）滤波器和发送数据寄存器。 锁相环包括数字粗回路和模拟精密回路。 数字接收机部分包含PLL，FIR相位旋转器，相位旋转器控制状态机和时钟缓冲器。 发射机和接收机各自优选地利用伪随机比特流（PRBS）生成器和检查器。
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10.发明授权Method and system for low-power integrating decision feedback equalizer with fast switched-capacitor feed forward path 失效具有快速开关电容器前馈路径的低功率积分判决反馈均衡器的方法和系统公开(公告)号：US07539243B1
公开(公告)日：2009-05-26
申请号：US12060140
申请日：2008-03-31
CPC分类号： H04L25/03057 , H04L2025/0349
摘要： A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.
摘要翻译： 提供了一种用于数字传输系统的判决反馈均衡的方法和系统。 使用具有快速开关电容路径的低功率积分判决反馈均衡，用于抑制由于过去的数据符号引起的符号间干扰（ISI）。 判定反馈均衡涉及在电流积分缓冲器的输出处采用快速电容耦合前馈路径的低功率执行电流积分判决反馈均衡，并通过耦合的开关电容器通过电荷再分配来感应电压变化，并且执行电压 数字到模拟对话，以确定反馈系数作为耦合电压。 然后，开关被复位到缓冲器中的预充电耦合电压，以消除由信号历史引起的剩余ISI，从而在积分期间实现电流积分缓冲与开关电容器反馈，并且电容开关由先前的符号触发。
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