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公开(公告)号：US08130887B2
公开(公告)日：2012-03-06
申请号：US12124106
申请日：2008-05-20
申请人： Hayden Clavie Cranford, Jr. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
发明人： Hayden Clavie Cranford, Jr. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/091 , H03L2207/50
摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.
摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。
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公开(公告)号：US06970529B2
公开(公告)日：2005-11-29
申请号：US09996113
申请日：2001-11-28
CPC分类号： H03L7/08 , H03L7/095 , H03L7/0995 , H03L7/10 , H04L7/0337 , H04L2027/0067
摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
摘要翻译： 描述了统一的单向串行链路，用于通过诸如芯片到芯片或卡到卡互连的有线介质提供数据。 它由一个传输部分和一个接收部分组成，它们被成对地运行以允许串行数据通信。 串行链路作为VLSI ASIC模块的一部分实现，并从主机模块中获得其功率，数据和时钟要求。 逻辑发送器部分包含锁相环（PLL），双位数据寄存器，有限脉冲响应（FIR）滤波器和发送数据寄存器。 锁相环包括数字粗回路和模拟精密回路。 数字接收机部分包含PLL，FIR相位旋转器，相位旋转器控制状态机和时钟缓冲器。 发射机和接收机各自优选地利用伪随机比特流（PRBS）生成器和检查器。
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公开(公告)号：US07646839B2
公开(公告)日：2010-01-12
申请号：US11249851
申请日：2005-10-13
IPC分类号： H03D3/24
CPC分类号： H03L7/08 , H03L7/095 , H03L7/0995 , H03L7/10 , H04L7/0337 , H04L2027/0067
摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
摘要翻译： 描述了统一的单向串行链路，用于通过诸如芯片到芯片或卡到卡互连的有线介质提供数据。 它由一个传输部分和一个接收部分组成，它们被成对地运行以允许串行数据通信。 串行链路作为VLSI ASIC模块的一部分实现，并从主机模块中获得其功率，数据和时钟要求。 逻辑发送器部分包含锁相环（PLL），双位数据寄存器，有限脉冲响应（FIR）滤波器和发送数据寄存器。 锁相环包括数字粗回路和模拟精密回路。 数字接收机部分包含PLL，FIR相位旋转器，相位旋转器控制状态机和时钟缓冲器。 发射机和接收机各自优选地利用伪随机比特流（PRBS）生成器和检查器。
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公开(公告)号：US07142624B2
公开(公告)日：2006-11-28
申请号：US11225600
申请日：2005-09-13
申请人： Hayden Clavie Cranford, Jr. , Stacy Jean Garvin , Vernon Roberts Norman , Paul Alan Owczarski , Martin Leo Schmatz , Joseph Marsh Stevens
发明人： Hayden Clavie Cranford, Jr. , Stacy Jean Garvin , Vernon Roberts Norman , Paul Alan Owczarski , Martin Leo Schmatz , Joseph Marsh Stevens
IPC分类号： H03D3/24
CPC分类号： H03L7/0995 , H04L7/0004 , H04L7/0337
摘要： The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.
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公开(公告)号：US06993107B2
公开(公告)日：2006-01-31
申请号：US09996053
申请日：2001-11-28
申请人： Hayden Clavie Cranford, Jr. , Stacy Jean Garvin , Vernon Roberts Norman , Paul Alan Owczarski , Martin Leo Schmatz , Joseph Marsh Stevens
发明人： Hayden Clavie Cranford, Jr. , Stacy Jean Garvin , Vernon Roberts Norman , Paul Alan Owczarski , Martin Leo Schmatz , Joseph Marsh Stevens
IPC分类号： H03D3/24
CPC分类号： H03L7/0995 , H04L7/0004 , H04L7/0337
摘要： A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver. The system comprises a phase locked loop (PLL) control circuit, a phase rotator circuit, a phase buffer circuit, and an equalization driver circuit. The phase rotator circuit is configured to acquire a clock phase from the phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop, a multi-stage voltage controlled oscillator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter. The fine loop includes the oscillator, a frequency divider, a phase-frequency detector, a charge pump and a loop filter.
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公开(公告)号：US07082484B2
公开(公告)日：2006-07-25
申请号：US09996091
申请日：2001-11-28
CPC分类号： G06F13/423
摘要： A global architecture for a serial link connection between two cards which must transmit data across wired media is provided. The architecture comprises a transmitter portion and a receiver portion. The transmitter portion includes a structure and circuitry to take digital bits from a first bit register, such as for example, an eight-bit register or a ten-bit register, and convert these bits into serial analog transmission to the receiver portion. The receiver portion includes a structure and circuitry to sample the analog transmission of the original digital bits and reconvert the analog serial signal of the digital bits corresponding to the original digital bits and store them in a second bit register comparable to the data stored in the original register from which they were selected.
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公开(公告)号：US06999544B2
公开(公告)日：2006-02-14
申请号：US09997587
申请日：2001-11-28
IPC分类号： H04L7/04
CPC分类号： H04L7/0337 , H03L7/06
摘要： The architecture and the method of operation of a receiver core are described. The core performs clock and data recovery on an incoming serial data stream transmitted across a wired media, such as a chip-to-chip or card-to-card interconnect. The bit error rate and accuracy of the recovery are optimized without centering of oversampling. Further, random errors due to edge mis-tracking are minimized. The receiver utilizes a phase rotator to detect the edge position of the bits of the data stream, select the optimum data sample and generate early and late signals if the detected edge is not in the expected position. A phase locked loop provides a frequency source for the phase rotator. At least three evenly spaced samples are detected for each bit. A sample processing algorithm, preferably an adaptive behavior algorithm, is used for centering the bit edge between two of the samples.
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公开(公告)号：US20080285695A1
公开(公告)日：2008-11-20
申请号：US12124106
申请日：2008-05-20
申请人： Hayden Clavie Cranford, JR. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
发明人： Hayden Clavie Cranford, JR. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/091 , H03L2207/50
摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.
摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。
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公开(公告)号：US07397876B2
公开(公告)日：2008-07-08
申请号：US10915790
申请日：2004-08-11
申请人： Hayden Clavie Cranford, Jr. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
发明人： Hayden Clavie Cranford, Jr. , Gareth John Nicholls , Vernon Roberts Norman , Martin Leo Schmatz , Karl David Selander , Michael Anthony Sorna
CPC分类号： H04L7/0337 , H03L7/091 , H03L2207/50
摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.
摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。
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公开(公告)号：US07692447B2
公开(公告)日：2010-04-06
申请号：US12115933
申请日：2008-05-06
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K17/164 , H04L25/0278 , H04L25/028
摘要： A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.
摘要翻译： 提供了驱动器电路，其包括至少两个相等的主单元（MU），每个主单元包括耦合到数据输出（dout）的至少两个子单元（SU）。 每个子单元（SU）适于表示相应的预定阻抗。 每个主单元（MU）适于当处于数据模式时，根据要发送的数据信号，各个主单元（MU）的每个子单元（SU）可切换到第一或第二参考电位。 每个主单元（MU）还适用于当处于终止模式时，相应主单元（MU）的子单元（SU）被切换到第一或第二参考电位，使得各个主单元（MU）的输出 单位（MU）相对于第一或第二参考电位的数据输出（dout）的驱动是中性的。
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