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    Method of Base Formation in a Bicmos Process
    1.
    发明申请
    Method of Base Formation in a Bicmos Process 有权
    Bicmos工艺中基体形成的方法

    公开(公告)号：US20070207567A1

    公开(公告)日：2007-09-06

    申请号：US10599938

    申请日：2005-04-06

    申请人： Peter Geiss ,  Alvin Joseph ,  Qizhi Liu ,  Bradley Orner

    发明人： Peter Geiss ,  Alvin Joseph ,  Qizhi Liu ,  Bradley Orner

    IPC分类号： H01L21/04 ,  H01L29/73

    CPC分类号： H01L29/0804 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

    摘要： Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

    摘要翻译： 公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极，集电极之上的本征基极，与集电极相邻的浅沟槽隔离区，在本征基极之上的凸起的外部基极，T形发射极 在外部基极之上，邻近发射极的间隔物和通过间隔物与发射极分离的硅化物层。

    Method of collector formation in BiCMOS technology
    3.
    发明申请
    Method of collector formation in BiCMOS technology 有权

    公开(公告)号：US20060124964A1

    公开(公告)日：2006-06-15

    申请号：US11288843

    申请日：2005-11-29

    申请人： Peter Geiss ,  Peter Gray ,  Alvin Joseph ,  Qizhi Liu

    发明人： Peter Geiss ,  Peter Gray ,  Alvin Joseph ,  Qizhi Liu

    IPC分类号： H01L31/109

    CPC分类号： H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

    摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

    Methods of base formation in a BiCMOS process
    5.
    发明申请
    Methods of base formation in a BiCMOS process 失效
    BiCMOS工艺中碱形成的方法

    公开(公告)号：US20060017066A1

    公开(公告)日：2006-01-26

    申请号：US11231385

    申请日：2005-09-21

    申请人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

    发明人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

    IPC分类号： H01L31/109

    CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

    摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

    摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

    High fT and fmax bipolar transistor and method of making same
    6.
    发明申请
    High fT and fmax bipolar transistor and method of making same 失效
    高fT和fmax双极晶体管及其制造方法

    公开(公告)号：US20060177986A1

    公开(公告)日：2006-08-10

    申请号：US11378927

    申请日：2006-03-17

    申请人： Alvin Joseph ,  Qizhi Liu

    发明人： Alvin Joseph ,  Qizhi Liu

    IPC分类号： H01L21/8222

    CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/732

    摘要： A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.

    摘要翻译： 高电平和高压双极晶体管包括发射极，基极和集电极。 发射器具有延伸超出下部的下部和上部。 基础包括内在基础和外在碱基。 本征基极位于发射极的下部和集电极之间。 外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体。 连续导体提供从底部触点（未示出）到本征基极的低电阻路径。 晶体管可以包括不延伸在发射极的上部下方的第二导体，但是通过外部基极进一步降低电阻。

    Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same
    7.
    发明申请
    Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 失效
    双极晶体管具有可选择的自对准的外部基极和其形成方法

    公开(公告)号：US20060081934A1

    公开(公告)日：2006-04-20

    申请号：US11289915

    申请日：2005-11-30

    申请人： Marwan Khater ,  James Dunn ,  David Harame ,  Alvin Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen Onge ,  Andreas Stricker

    发明人： Marwan Khater ,  James Dunn ,  David Harame ,  Alvin Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen Onge ,  Andreas Stricker

    IPC分类号： H01L23/62

    CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

    摘要翻译： 公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。 制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。 然后通过在第一非本征基层上的光刻形成电介质着色焊盘。 接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。 通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

    METHOD TO BUILD SELF-ALIGNED NPN IN ADVANCED BiCMOS TECHNOLOGY
    8.
    发明申请
    METHOD TO BUILD SELF-ALIGNED NPN IN ADVANCED BiCMOS TECHNOLOGY 失效
    在高级BiCMOS技术中构建自对准NPN的方法

    公开(公告)号：US20070264787A1

    公开(公告)日：2007-11-15

    申请号：US11830376

    申请日：2007-07-30

    申请人： James Dunn ,  Alvin Joseph ,  Qizhi Liu

    发明人： James Dunn ,  Alvin Joseph ,  Qizhi Liu

    IPC分类号： H01L21/331

    CPC分类号： H01L29/66242 ,  H01L29/7378

    摘要： The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.

    摘要翻译： 本发明提供了一种在BiCMOS技术中形成自对准异双极晶体管（HBT）器件的方法。 该方法包括通过使用其中单晶硅和多晶硅的生长速率不同的外延生长工艺和通过使用诸如高压氧化（HIPOX）工艺的低温氧化工艺形成凸起的外在基体结构来形成 自对准发射极/非本征基极HBT结构。

    METHOD TO BUILD SELF-ALIGNED NPN IN ADVANCED BiCMOS TECHNOLOGY
    9.
    发明申请
    METHOD TO BUILD SELF-ALIGNED NPN IN ADVANCED BiCMOS TECHNOLOGY 有权
    在高级BiCMOS技术中构建自对准NPN的方法

    公开(公告)号：US20060060886A1

    公开(公告)日：2006-03-23

    申请号：US10711486

    申请日：2004-09-21

    申请人： James Dunn ,  Alvin Joseph ,  Qizhi Liu

    发明人： James Dunn ,  Alvin Joseph ,  Qizhi Liu

    IPC分类号： H01L29/737 ,  H01L21/331

    CPC分类号： H01L29/66242 ,  H01L29/7378

    摘要： The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.

    摘要翻译： 本发明提供了一种在BiCMOS技术中形成自对准异双极晶体管（HBT）器件的方法。 该方法包括通过使用其中单晶硅和多晶硅的生长速率不同的外延生长工艺和通过使用诸如高压氧化（HIPOX）工艺的低温氧化工艺形成凸起的外在基体结构来形成 自对准发射极/非本征基极HBT结构。

    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME
    10.
    发明申请
    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 有权
    通过VIAS的低电阻和电感及其制造方法

    公开(公告)号：US20070190692A1

    公开(公告)日：2007-08-16

    申请号：US11275542

    申请日：2006-01-13

    申请人： Mete Erturk ,  Robert Groves ,  Jeffrey Johnson ,  Alvin Joseph ,  Qizhi Liu ,  Edmund Sprogis ,  Anthony Stamper

    发明人： Mete Erturk ,  Robert Groves ,  Jeffrey Johnson ,  Alvin Joseph ,  Qizhi Liu ,  Edmund Sprogis ,  Anthony Stamper

    IPC分类号： H01L21/50

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

    摘要翻译： 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔离; 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。