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    Methods of base formation in a BiCMOS process
    1.
    发明申请
    Methods of base formation in a BiCMOS process 失效
    BiCMOS工艺中碱形成的方法

    公开(公告)号：US20060017066A1

    公开(公告)日：2006-01-26

    申请号：US11231385

    申请日：2005-09-21

    申请人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

    发明人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

    IPC分类号： H01L31/109

    CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

    摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

    摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

    ISOLATED FULLY DEPLETED SILICON-ON-INSULATOR REGIONS BY SELECTIVE ETCH
    3.
    发明申请
    ISOLATED FULLY DEPLETED SILICON-ON-INSULATOR REGIONS BY SELECTIVE ETCH 审中-公开
    通过选择性蚀刻分离完全绝缘的绝缘体绝缘体区域

    公开(公告)号：US20070128776A1

    公开(公告)日：2007-06-07

    申请号：US11670262

    申请日：2007-02-01

    申请人： Matthew Breitwisch ,  Chung Lam ,  Randy Mann ,  Dale Martin

    发明人： Matthew Breitwisch ,  Chung Lam ,  Randy Mann ,  Dale Martin

    IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/00

    CPC分类号： H01L21/764 ,  H01L21/76283 ,  H01L21/76289 ,  H01L29/78654

    摘要： The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.

    摘要翻译： 本发明提供一种形成超薄且均匀的Si层的方法，包括以下步骤：提供具有由绝缘区分隔开的半导体区域的衬底; 将掺杂剂注入衬底中以在半导体区域的上部含Si表面下方的半导体区域中提供蚀刻差分掺杂部分; 在包括半导体区域和绝缘区域的衬底中形成沟槽; 从所述半导体区域去除所述蚀刻差分掺杂部分以在所述半导体区域的上表面下方形成空腔; 以及用沟槽电介质填充所述沟槽，其中所述沟槽电介质材料包围在所述半导体区域的所述上部含Si表面之下的空腔。 半导体区域的上部含Si表面具有小于约的均匀厚度。

    INTEGRATED CIRCUIT WITH A FIN-BASED FUSE, AND RELATED FABRICATION METHOD
    5.
    发明申请
    INTEGRATED CIRCUIT WITH A FIN-BASED FUSE, AND RELATED FABRICATION METHOD 有权
    具有熔点熔丝的集成电路及相关制造方法

    公开(公告)号：US20130001741A1

    公开(公告)日：2013-01-03

    申请号：US13171228

    申请日：2011-06-28

    申请人： Randy Mann ,  Kingsuk Maitra ,  Anurag Mittal

    发明人： Randy Mann ,  Kingsuk Maitra ,  Anurag Mittal

    IPC分类号： H01L23/52 ,  H01L21/20

    CPC分类号： H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

    摘要翻译： 提供了制造具有鳍式保险丝的集成电路的方法，以及所得到的具有鳍式保险丝的集成电路。 在该方法中，由半导体材料层产生翅片并具有第一端和第二端。 该方法提供了在翅片上从其第一端到其第二端形成导电路径。 导电路径电连接到编程设备，该编程设备能够选择性地将编程电流引导通过导电路径，从而导致导电路径中的结构变化，以增加穿过导电路径的电阻。

    SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS
    6.
    发明申请
    SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS 有权
    用于改进操作标准的SRAM电压控制

    公开(公告)号：US20070121370A1

    公开(公告)日：2007-05-31

    申请号：US11164556

    申请日：2005-11-29

    申请人： Wayne Ellis ,  Randy Mann ,  David Wager ,  Robert Wong

    发明人： Wayne Ellis ,  Randy Mann ,  David Wager ,  Robert Wong

    IPC分类号： G11C11/00

    CPC分类号： G11C5/14 ,  G11C11/413

    摘要： A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

    摘要翻译： 提供了包括以阵列布置的多个SRAM单元的静态随机存取存储器（“SRAM”）。 阵列包括多个行和多个列。 SRAM包括对应于阵列的多个列中的相应列的多个电压控制。 多个电压控制电路中的每一个耦合到电源的输出，每个电压控制电路具有临时降低提供给属于所选列列的多个SRAM单元的电源输入的电压的功能 SRAM。 选择的列被选择，并且在将位写入属于所选列的SRAM单元之一的写操作期间，该列的电源电压减小。

    Semiconductor Integrated Test Structures For Electron Beam Inspection of Semiconductor Wafers
    7.
    发明申请
    Semiconductor Integrated Test Structures For Electron Beam Inspection of Semiconductor Wafers 有权
    用于半导体晶片的电子束检测的半导体集成测试结构

    公开(公告)号：US20080237586A1

    公开(公告)日：2008-10-02

    申请号：US11694449

    申请日：2007-03-30

    申请人： Min Chul Sun ,  Scott Jansen ,  Randy Mann ,  Oliver D. Patterson

    发明人： Min Chul Sun ,  Scott Jansen ,  Randy Mann ,  Oliver D. Patterson

    IPC分类号： H01L23/58 ,  H01L21/66

    CPC分类号： H01L22/32

    摘要： Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.

    摘要翻译： 半导体集成测试结构被设计用于半导体晶片的电子束检查。 测试结构包括与晶片上形成的集成电路的图形特征同时形成在晶片的指定测试区域中的图案特征。 测试结构包括导电结构，其被设计成能够在缺陷和非缺陷特征（或给定特征的有缺陷和非缺陷部分）之间进行差分充电，以便于CMOS器件的电压对比度缺陷检测，例如使用单个， 尽管晶片衬底或其他元件/特征中存在p / n结，但是低能电子束扫描也是如此。

    Isolated fully depleted silicon-on-insulator regions by selective etch
    9.
    发明申请
    Isolated fully depleted silicon-on-insulator regions by selective etch 失效
    通过选择性蚀刻隔离完全耗尽的绝缘体上硅区域

    公开(公告)号：US20060027889A1

    公开(公告)日：2006-02-09

    申请号：US10710821

    申请日：2004-08-05

    申请人： Matthew Breitwisch ,  Chung Lam ,  Randy Mann ,  Dale Martin

    发明人： Matthew Breitwisch ,  Chung Lam ,  Randy Mann ,  Dale Martin

    IPC分类号： H01L29/06 ,  H01L21/76

    CPC分类号： H01L21/764 ,  H01L21/76283 ,  H01L21/76289 ,  H01L29/78654

    摘要： The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.

    摘要翻译： 本发明提供一种形成超薄且均匀的Si层的方法，包括以下步骤：提供具有由绝缘区分隔开的半导体区域的衬底; 将掺杂剂注入衬底中以在半导体区域的上部含Si表面下方的半导体区域中提供蚀刻差分掺杂部分; 在包括半导体区域和绝缘区域的衬底中形成沟槽; 从所述半导体区域移除所述蚀刻差分掺杂部分以产生位于所述半导体区域的上表面下方的空腔; 以及用沟槽电介质填充所述沟槽，其中所述沟槽电介质材料包围在所述半导体区域的所述上部含Si表面下面的空腔。 半导体区域的上部含Si表面具有小于约的均匀厚度。