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    Process for making an EEPROM active area castling
    1.
    发明授权
    Process for making an EEPROM active area castling 失效
    制造EEPROM活动区域铸造的过程

    公开(公告)号：US06187634B1

    公开(公告)日：2001-02-13

    申请号：US09045737

    申请日：1998-03-19

    申请人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    发明人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    IPC分类号： H01L21336

    CPC分类号： H01L27/11519 ,  H01L27/0203 ,  Y10S438/942

    摘要： Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

    摘要翻译： 提供了一个“castled”活动区域面罩。 壁挂式有源区掩模是延长超过其与隧道电介质的预期交点的形式的有源区掩模，以形成EEPROM单元的隧道窗口，并且还在扩展的至少一部分中加宽。 例如，在一个优选实施例中，城堡延伸部可以具有“T”形状。 由这种掩模产生的拱形有源区域在到达EEPROM单元的TD窗口之前提供缓冲器以吸收场氧化物侵入。 根据本发明的掩模可以用于制造由于场氧化物侵入而不受TD窗口尺寸变化的EEPROM单元以及增加密度的EEPROM单元阵列。

    EEPROM active area castling
    2.
    发明授权
    EEPROM active area castling 失效
    EEPROM活动区域

    公开(公告)号：US06624467B1

    公开(公告)日：2003-09-23

    申请号：US10193085

    申请日：2002-07-09

    申请人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    发明人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    IPC分类号： H01L29788

    CPC分类号： H01L27/11519 ,  H01L27/0203

    摘要： Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

    摘要翻译： 提供了一个“castled”活动区域面罩。 壁挂式有源区掩模是延长超过其与隧道电介质的预期交点的形式的有源区掩模，以形成EEPROM单元的隧道窗口，并且还在扩展的至少一部分中加宽。 例如，在一个优选实施例中，城堡延伸部可以具有“T”形。 由这种掩模产生的拱形有源区域在到达EEPROM单元的TD窗口之前提供缓冲器以吸收场氧化物侵入。 根据本发明的掩模可以用于制造由于场氧化物侵入而不受TD窗口尺寸变化的EEPROM单元以及增加密度的EEPROM单元阵列。

    Castled active area mask
    3.
    发明授权
    Castled active area mask 失效
    壁挂活动区域面罩

    公开(公告)号：US06472272B1

    公开(公告)日：2002-10-29

    申请号：US09733850

    申请日：2000-12-08

    申请人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    发明人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    IPC分类号： H01L21336

    CPC分类号： H01L27/11519 ,  H01L27/0203 ,  Y10S438/942

    摘要： Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

    摘要翻译： 提供了一个“castled”活动区域面罩。 壁挂式有源区掩模是延长超过其与隧道电介质的预期交点的形式的有源区掩模，以形成EEPROM单元的隧道窗口，并且还在扩展的至少一部分中加宽。 例如，在一个优选实施例中，城堡延伸部可以具有“T”形状。 由这种掩模产生的拱形有源区域在到达EEPROM单元的TD窗口之前提供缓冲器以吸收场氧化物侵入。 根据本发明的掩模可以用于制造由于场氧化物侵入而不受TD窗口尺寸变化的EEPROM单元以及增加密度的EEPROM单元阵列。

    Method for implementing electro-static discharge protection in silicon-on-insulator devices
    5.
    发明授权
    Method for implementing electro-static discharge protection in silicon-on-insulator devices 有权
    在绝缘体上硅器件中实施静电放电保护的方法

    公开(公告)号：US07125760B1

    公开(公告)日：2006-10-24

    申请号：US11117904

    申请日：2005-04-29

    申请人： Dirk Alan Reese ,  Peter McElheny ,  Minchang Liang

    发明人： Dirk Alan Reese ,  Peter McElheny ,  Minchang Liang

    IPC分类号： H01L21/84

    CPC分类号： H01L27/0266

    摘要： The present invention is a method and apparatus whereby two NMOS or PMOS devices connected in series in a stacked gate configuration formed on SOI exhibit improved ESD response characteristics. The shared source-drain region between the two devices is formed to have a dopant depth in the shared region that does not extend through the silicon layer to the BOX layer. This provides a common body for the two devices, and thus a single parasitic bipolar transistor is formed between the drain of one NMOS or PMOS device and the source of the second NMOS or PMOS device. Simultaneous snapback occurs for the two devices through the common body. A further embodiment includes a method of forming two or more stacked gate NMOS or PMOS devices on SOI. The method includes protecting the shared source-drain region between two NMOS or PMOS devices during a final doping step and silicide processing.

    摘要翻译： 本发明是一种方法和装置，其中形成在SOI上的堆叠栅极配置中串联连接的两个NMOS或PMOS器件表现出改进的ESD响应特性。 两个器件之间的共享源极 - 漏极区域形成为在共享区域中具有不延伸穿过硅层到BOX层的掺杂剂深度。 这为两个器件提供了一个共同体，因此在一个NMOS或PMOS器件的漏极和第二个NMOS或PMOS器件的源极之间形成单个寄生双极晶体管。 两台设备通过通用主机同时发生回跳。 另一实施例包括在SOI上形成两个或多个层叠栅极NMOS或PMOS器件的方法。 该方法包括在最终掺杂步骤和硅化物处理期间保护两个NMOS或PMOS器件之间的共享源极 - 漏极区域。

    Bipolar transistors with low base resistance for CMOS integrated circuits
    6.
    发明授权
    Bipolar transistors with low base resistance for CMOS integrated circuits 有权
    用于CMOS集成电路的具有低基极电阻的双极晶体管

    公开(公告)号：US07285454B1

    公开(公告)日：2007-10-23

    申请号：US11207461

    申请日：2005-08-19

    申请人： Minchang Liang ,  Yow-Juang Liu ,  Fangyun Richter

    发明人： Minchang Liang ,  Yow-Juang Liu ,  Fangyun Richter

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/735

    摘要： Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.

    摘要翻译： 提供了具有双极晶体管的互补金属氧化物半导体（CMOS）集成电路及其制造方法。 双极晶体管可以具有轻掺杂的基极区域。 为了减小与轻掺杂基极区域的电接触相关联的电阻，可以提供进入基极区域的低电阻电流通路。 低电阻电流路径可以由由重掺杂外延晶体半导体形成的基极导体提供。 具有窄栅极的金属氧化物半导体（MOS）晶体管可以形成在与双极晶体管相同的衬底上。 可以使用自对准工艺来形成MOS栅极，其中图案化的栅极导体层用作注入掩模和栅极导体。 可以将与图案化的栅极导体层分离的基底掩模层用作用于限定轻掺杂基极区域的注入掩模。

    Bipolar transistors with low base resistance for CMOS integrated circuits
    7.
    发明授权
    Bipolar transistors with low base resistance for CMOS integrated circuits 失效
    用于CMOS集成电路的具有低基极电阻的双极晶体管

    公开(公告)号：US06972466B1

    公开(公告)日：2005-12-06

    申请号：US10784417

    申请日：2004-02-23

    申请人： Minchang Liang ,  Yow-Juang Liu ,  Fangyun Richter

    发明人： Minchang Liang ,  Yow-Juang Liu ,  Fangyun Richter

    IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/735 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/735

    摘要： Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.

    摘要翻译： 提供了具有双极晶体管的互补金属氧化物半导体（CMOS）集成电路及其制造方法。 双极晶体管可以具有轻掺杂的基极区域。 为了减小与轻掺杂基极区域的电接触相关联的电阻，可以提供进入基极区域的低电阻电流通路。 低电阻电流路径可以由由重掺杂外延晶体半导体形成的基极导体提供。 具有窄栅极的金属氧化物半导体（MOS）晶体管可以形成在与双极晶体管相同的衬底上。 可以使用自对准工艺来形成MOS栅极，其中图案化的栅极导体层用作注入掩模和栅极导体。 可以将与图案化的栅极导体层分离的基底掩模层用作用于限定轻掺杂基极区域的注入掩模。

    Method of semiconductor integrated circuit fabrication
    9.
    发明授权
    Method of semiconductor integrated circuit fabrication 有权
    半导体集成电路制造方法

    公开(公告)号：US08937006B2

    公开(公告)日：2015-01-20

    申请号：US13561263

    申请日：2012-07-30

    申请人： Minchang Liang ,  Chie-Iuan Lin ,  Yao-Kwang Wu

    发明人： Minchang Liang ,  Chie-Iuan Lin ,  Yao-Kwang Wu

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/76897 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/66545

    摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device. The method also includes forming a step-forming-hard-mask (SFHM) on the MG stack in a predetermined area on the semiconductor substrate, performing MG recessing, depositing a MG hard mask over the semiconductor substrate and recessing the MG hard mask to fully remove the MG hard mask from the MG stack in the predetermined area.

    摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括接收半导体器件。 该方法还包括在半导体衬底上的预定区域中的MG堆叠上形成阶梯形成 - 硬掩模（SFHM），执行MG凹陷，在半导体衬底上沉积MG硬掩模并使MG硬掩模完全凹陷 从预定区域的MG堆叠中取出MG硬掩模。